1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
|
chip soc/intel/cannonlake
# FSP configuration
register "SataMode" = "0" # AHCI
register "SataSalpSupport" = "0"
register "satapwroptimize" = "1"
register "SataPortsDevSlp[1]" = "1" # PCH_M2_SATA_DEVSLP1
register "SataPortsEnable[0]" = "1"
register "SataPortsEnable[1]" = "1" # depends on SATAXPCIE1
register "SataPortsEnable[2]" = "0" # Not used for SATA
register "SataPortsEnable[3]" = "0" # Not used for SATA
register "SataPortsEnable[4]" = "1"
register "SataPortsEnable[5]" = "1"
register "SataPortsEnable[6]" = "1"
register "SataPortsEnable[7]" = "1"
register "SataPortsHotPlug[0]" = "1"
register "SataPortsHotPlug[1]" = "1"
register "SataPortsHotPlug[2]" = "0"
register "SataPortsHotPlug[3]" = "0"
register "SataPortsHotPlug[4]" = "1"
register "SataPortsHotPlug[5]" = "1"
register "SataPortsHotPlug[6]" = "1"
register "SataPortsHotPlug[7]" = "1"
register "PchHdaDspEnable" = "0"
register "PchHdaAudioLinkHda" = "1"
register "PcieClkSrcUsage[0]" = "20" # PCIe Slot1
register "PcieClkSrcUsage[1]" = "0x40" # PCIe Slot2
register "PcieClkSrcUsage[2]" = "0x42" # PCIe Slot4
register "PcieClkSrcUsage[3]" = "0x41" # PCIe Slot6
register "PcieClkSrcUsage[4]" = "8" # RP9 M2 Slot M x4
register "PcieClkSrcUsage[5]" = "15" # RP16 M2 Slot E x1
register "PcieClkSrcUsage[6]" = "14" # BMC
register "PcieClkSrcUsage[7]" = "4" # PHY 3
register "PcieClkSrcUsage[8]" = "PCIE_CLK_RP0" # PCIe Slot3
register "PcieClkSrcUsage[9]" = "5" # PHY 4
register "PcieClkSrcUsage[10]" = "6" # PHY 2
register "PcieClkSrcUsage[11]" = "7" # PHY 1
register "PcieClkSrcUsage[12]" = "13" # PHY 0
register "PcieClkSrcUsage[13]" = "0x42" # PB
register "PcieClkSrcUsage[14]" = "PCIE_CLK_NOTUSED"
register "PcieClkSrcUsage[15]" = "PCIE_CLK_NOTUSED"
# Only enable CLKREQ# for M.2 slots
register "PcieClkSrcClkReq[0]" = "PCIE_CLK_NOTUSED"
register "PcieClkSrcClkReq[1]" = "PCIE_CLK_NOTUSED"
register "PcieClkSrcClkReq[2]" = "PCIE_CLK_NOTUSED"
register "PcieClkSrcClkReq[3]" = "PCIE_CLK_NOTUSED"
register "PcieClkSrcClkReq[4]" = "4" # M2_M_CLK_REQ_n
register "PcieClkSrcClkReq[5]" = "5" # M2_E_CLK_REQ_n
register "PcieClkSrcClkReq[6]" = "PCIE_CLK_NOTUSED"
register "PcieClkSrcClkReq[7]" = "PCIE_CLK_NOTUSED"
register "PcieClkSrcClkReq[8]" = "PCIE_CLK_NOTUSED"
register "PcieClkSrcClkReq[9]" = "PCIE_CLK_NOTUSED"
register "PcieClkSrcClkReq[10]" = "PCIE_CLK_NOTUSED"
register "PcieClkSrcClkReq[11]" = "PCIE_CLK_NOTUSED"
register "PcieClkSrcClkReq[12]" = "PCIE_CLK_NOTUSED"
register "PcieClkSrcClkReq[13]" = "PCIE_CLK_NOTUSED"
# USB OC5-7: not connected
register "usb2_ports" = "{
#define HERMES_USB2_CONFIG(pin) { \
.enable = 1, \
.ocpin = (pin), \
.tx_bias = USB2_BIAS_0MV, \
.tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON, \
.pre_emp_bias = USB2_BIAS_28P15MV, \
.pre_emp_bit = USB2_FULL_BIT_PRE_EMP, \
}
[0] = HERMES_USB2_CONFIG(OC0), /* USB3 rear panel 1 */
[1] = HERMES_USB2_CONFIG(OC0),
[2] = HERMES_USB2_CONFIG(OC1), /* USB3 rear panel 2 */
[3] = HERMES_USB2_CONFIG(OC1),
[4] = HERMES_USB2_CONFIG(OC2), /* USB3 internal header CN_USB3_HDR */
[5] = HERMES_USB2_CONFIG(OC2),
[6] = HERMES_USB2_CONFIG(OC3), /* USB2 internal header USB2_HDR1 */
[7] = HERMES_USB2_CONFIG(OC3),
[8] = HERMES_USB2_CONFIG(OC4), /* USB2 internal header USB2_HDR1 */
[9] = HERMES_USB2_CONFIG(OC4),
[10] = HERMES_USB2_CONFIG(OC_SKIP), /* BMC */
[11] = USB2_PORT_EMPTY,
[12] = HERMES_USB2_CONFIG(OC_SKIP), /* piggy-back */
[13] = HERMES_USB2_CONFIG(OC_SKIP), /* M.2 key E */
}"
# USB Config 2.0/3.0
# Enumeration starts at 0
# USB 3.0
# USB OC0: RP1
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"
# USB OC1: RP2
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)"
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)"
# USB OC2: Internal Header CN_USB3_HDR
register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)"
register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC2)"
# Thermal
register "tcc_offset" = "1" # TCC of 99C
# Disable S0ix
register "s0ix_enable" = "0"
# Enable Turbo
register "eist_enable" = "1"
register "common_soc_config" = "{
.gspi[0] = {
.speed_mhz = 1,
.early_init = 1,
},
}"
# VR Power Delivery Design
register "VrPowerDeliveryDesign" = "0x12"
register "SerialIoDevMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoDisabled,
[PchSerialIoIndexI2C1] = PchSerialIoDisabled,
[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
[PchSerialIoIndexSPI0] = PchSerialIoPci,
[PchSerialIoIndexSPI1] = PchSerialIoDisabled,
[PchSerialIoIndexUART0] = PchSerialIoPci,
[PchSerialIoIndexUART1] = PchSerialIoPci,
[PchSerialIoIndexUART2] = PchSerialIoPci,
}"
register "DisableHeciRetry" = "1"
device cpu_cluster 0 on
device lapic 0 on end
end
device domain 0 on
device pci 00.0 on end # Host Bridge
device pci 01.0 on # PEG x8 / Slot 2
smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT2" "SlotDataBusWidth8X"
end
device pci 01.1 on # PEG x4 or x8 / Slot 6
smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT6" "SlotDataBusWidth4X"
end
device pci 01.2 on # PEG x4 or disabled / Slot 4
smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT4" "SlotDataBusWidth4X"
end
device pci 02.0 on end # Integrated Graphics Device
device pci 04.0 on end # SA Thermal device
device pci 08.0 on end # Gaussian Mixture
device pci 12.0 on end # Thermal Subsystem
device pci 14.0 on end # USB xHCI
device pci 14.1 off end # USB xDCI (OTG)
device pci 14.2 on end # RAM controller
device pci 14.3 on
chip drivers/wifi/generic
register "wake" = "PME_B0_EN_BIT"
device generic 0 on end
end
end # CNVi wifi
device pci 14.5 off end # SDCard
device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 on end # Management Engine Interface 2
device pci 16.4 off end # Management Engine Interface 3
device pci 17.0 on end # SATA
# This device does not have any function on CNP-H, but it needs
# to be here so that the resource allocator is aware of UART 2.
device pci 19.0 hidden end
chip soc/intel/common/block/uart
device pci 19.2 hidden
register "devid" = "PCI_DEVICE_ID_INTEL_CNP_H_UART2"
end # UART #2, in ACPI mode
end
device pci 1b.4 on # PCIe root port 21 (Slot 1)
smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT1" "SlotDataBusWidth4X"
register "PcieRpEnable[20]" = "1"
register "PcieRpLtrEnable[20]" = "1"
register "PcieRpSlotImplemented[20]" = "1"
register "PcieRpMaxPayload[20]" = "RpMaxPayload_256"
register "PcieRpAdvancedErrorReporting[20]" = "1"
register "PcieRpAspm[20]" = "AspmDisabled"
end
device pci 1c.0 on # PCIe root port 1 (Slot 3)
smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT3" "SlotDataBusWidth4X"
register "PcieRpEnable[0]" = "1"
register "PcieRpLtrEnable[0]" = "1"
register "PcieRpSlotImplemented[0]" = "1"
register "PcieRpMaxPayload[0]" = "RpMaxPayload_256"
register "PcieRpAdvancedErrorReporting[0]" = "1"
register "PcieRpAspm[0]" = "AspmDisabled"
end
device pci 1c.4 on # PCIe root port 5 (PHY 3)
register "PcieRpEnable[4]" = "1"
register "PcieRpLtrEnable[4]" = "1"
end
device pci 1c.5 on # PCIe root port 6 (PHY 4)
register "PcieRpEnable[5]" = "1"
register "PcieRpLtrEnable[5]" = "1"
end
device pci 1c.6 on # PCIe root port 7 (PHY 2)
register "PcieRpEnable[6]" = "1"
register "PcieRpLtrEnable[6]" = "1"
end
device pci 1c.7 on # PCIe root port 8 (PHY 1)
register "PcieRpEnable[7]" = "1"
register "PcieRpLtrEnable[7]" = "1"
end
device pci 1d.0 on # PCIe root port 9 (M2 M)
smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "M2 M" "SlotDataBusWidth4X"
register "PcieRpEnable[8]" = "1"
register "PcieRpLtrEnable[8]" = "1"
register "PcieRpSlotImplemented[8]" = "1"
end
device pci 1d.5 on # PCIe root port 14 (PHY 0)
register "PcieRpEnable[13]" = "1"
register "PcieRpLtrEnable[13]" = "1"
end
device pci 1d.6 on # PCIe root port 15 (BMC)
device pci 00.0 on # Aspeed PCI Bridge
device pci 00.0 on end # Aspeed 2500 VGA
end
register "PcieRpEnable[14]" = "1"
register "PcieRpLtrEnable[14]" = "1"
register "PcieRpSlotImplemented[14]" = "1"
end
device pci 1d.7 on # PCIe root port 16 (M.2 E/CNVi)
# Disabled when CNVi is present
register "PcieRpEnable[15]" = "1"
register "PcieRpLtrEnable[15]" = "1"
register "PcieRpSlotImplemented[15]" = "1"
end
device pci 1e.0 on end # UART #0
device pci 1e.1 on end # UART #1
device pci 1e.2 off end # GSPI #0
device pci 1e.3 off end # GSPI #1
device pci 1f.0 on # LPC Interface
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end
# AST2500, but not enabled to decode LPC cycles
end
device pci 1f.1 on end # P2SB
device pci 1f.2 hidden end # Power Management Controller
device pci 1f.3 on end # Intel HDA
device pci 1f.4 on end # SMBus
device pci 1f.5 on end # PCH SPI
end
end
|
