blob: c5a03d131c4ffff39f93ed097ca83b6278e7c4e6 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
|
#
# This file is part of the coreboot project.
#
# Copyright (C) 2012 Advanced Micro Devices, Inc.
# Copyright (C) 2015 Kyösti Mälkki <kyosti.malkki@gmail.com>
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
if BOARD_PCENGINES_APU2 || BOARD_PCENGINES_APU3 || BOARD_PCENGINES_APU4 || \
BOARD_PCENGINES_APU5
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select BINARYPI_LEGACY_WRAPPER
select CPU_AMD_PI_00730F01
select NORTHBRIDGE_AMD_PI_00730F01
select SOUTHBRIDGE_AMD_PI_AVALON
select SUPERIO_NUVOTON_NCT5104D
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_8192
select HUDSON_DISABLE_IMC
select USE_BLOBS
select GENERIC_SPD_BIN
select MAINBOARD_HAS_LPC_TPM
select MAINBOARD_HAS_TPM1
select SEABIOS_ADD_SERCON_PORT_FILE if PAYLOAD_SEABIOS
config MAINBOARD_DIR
string
default pcengines/apu2
config VARIANT_DIR
string
default "apu2" if BOARD_PCENGINES_APU2
default "apu3" if BOARD_PCENGINES_APU3
default "apu4" if BOARD_PCENGINES_APU4
default "apu5" if BOARD_PCENGINES_APU5
config DEVICETREE
string
default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb"
config MAINBOARD_PART_NUMBER
string
default "apu2" if BOARD_PCENGINES_APU2
default "apu3" if BOARD_PCENGINES_APU3
default "apu4" if BOARD_PCENGINES_APU4
default "apu5" if BOARD_PCENGINES_APU5
config MAX_CPUS
int
default 4
config IRQ_SLOT_COUNT
int
default 11
config ONBOARD_VGA_IS_PRIMARY
bool
default y
config HUDSON_LEGACY_FREE
bool
default y
config AGESA_BINARY_PI_FILE
string
default "3rdparty/blobs/mainboard/pcengines/apu2/AGESA.bin"
choice
prompt "J19 pins 1-10"
default APU2_PINMUX_OFF_C if BOARD_PCENGINES_APU2 || \
BOARD_PCENGINES_APU3 || BOARD_PCENGINES_APU4
default APU2_PINMUX_UART_C if BOARD_PCENGINES_APU5
config APU2_PINMUX_OFF_C
bool "disable"
config APU2_PINMUX_GPIO0
bool "GPIO"
depends on BOARD_PCENGINES_APU2 || BOARD_PCENGINES_APU3 || \
BOARD_PCENGINES_APU4
config APU2_PINMUX_UART_C
bool "UART 0x3e8"
endchoice
choice
prompt "J19 pins 11-20"
default APU2_PINMUX_OFF_D if BOARD_PCENGINES_APU2 || \
BOARD_PCENGINES_APU3 || BOARD_PCENGINES_APU4
default APU2_PINMUX_UART_D if BOARD_PCENGINES_APU5
config APU2_PINMUX_OFF_D
bool "disable"
config APU2_PINMUX_GPIO1
bool "GPIO"
depends on BOARD_PCENGINES_APU2 || BOARD_PCENGINES_APU3 || \
BOARD_PCENGINES_APU4
config APU2_PINMUX_UART_D
bool "UART 0x2e8"
endchoice
config DIMM_SPD_SIZE
int
default 128
endif # BOARD_PCENGINES_APU2
|
