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#
# This file is part of the coreboot project.
#
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
if BOARD_PCENGINES_APU1
config BOARD_SPECIFIC_OPTIONS
def_bool y
select CPU_AMD_AGESA_FAMILY14
select NORTHBRIDGE_AMD_AGESA_FAMILY14
select SOUTHBRIDGE_AMD_CIMX_SB800
select SUPERIO_NUVOTON_NCT5104D
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select HAVE_OPTION_TABLE
select HAVE_CMOS_DEFAULT
select BOARD_ROMSIZE_KB_2048
select GENERIC_SPD_BIN
select SEABIOS_ADD_SERCON_PORT_FILE if PAYLOAD_SEABIOS
select MAINBOARD_HAS_LPC_TPM
config MAINBOARD_DIR
string
default "pcengines/apu1"
config MAINBOARD_PART_NUMBER
string
default "apu1"
config HW_MEM_HOLE_SIZEK
hex
default 0x200000
config MAX_CPUS
int
default 2
config IRQ_SLOT_COUNT
int
default 11
config ONBOARD_VGA_IS_PRIMARY
bool
default y
config VGA_BIOS
bool
default n
#config VGA_BIOS_FILE
# string "VGA BIOS path and filename"
# depends on VGA_BIOS
# default "rom/video/OntarioGenericVbios.bin"
config VGA_BIOS_ID
string
default "1002,9802"
config SB800_AHCI_ROM
bool
default n
config DRIVERS_PS2_KEYBOARD
bool
default n
choice
prompt "J19 pins 1-10"
default APU1_PINMUX_OFF_C
config APU1_PINMUX_OFF_C
bool "disable"
config APU1_PINMUX_GPIO0
bool "GPIO"
config APU1_PINMUX_UART_C
bool "UART 0x3e8"
endchoice
config UART_C_RS485
bool "UART C drives RTS# in RS485 mode" if APU1_PINMUX_UART_C
choice
prompt "J19 pins 11-20"
default APU1_PINMUX_OFF_D
config APU1_PINMUX_OFF_D
bool "disable"
config APU1_PINMUX_GPIO1
bool "GPIO"
config APU1_PINMUX_UART_D
bool "UART 0x2e8"
endchoice
config UART_D_RS485
bool "UART D drives RTS# in RS485 mode" if APU1_PINMUX_UART_D
config DIMM_SPD_SIZE
int
default 128
endif # BOARD_PCENGINES_APU1
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