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##
## This file is part of the coreboot project.
##
## Copyright (C) 2006 AMD
## Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
##
## Copyright (C) 2006 MSI
## Written by bxshi <bingxunshi@gmail.com> for MSI.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
## CONFIG_XIP_ROM_SIZE must be a power of 2.
default CONFIG_XIP_ROM_SIZE = 64 * 1024
include /config/nofailovercalculation.lb
arch i386 end
##
## Build the objects we have code for in this directory.
##
driver mainboard.o
#dir /drivers/si/3114
#needed by irq_tables and mptable and acpi_tables
object get_bus_conf.o
if CONFIG_GENERATE_MP_TABLE
object mptable.o
end
if CONFIG_GENERATE_PIRQ_TABLE
object irq_tables.o
end
if CONFIG_USE_INIT
# compile cache_as_ram.c to auto.o
makerule ./cache_as_ram_auto.o
depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
end
else
#compile cache_as_ram.c to auto.inc
makerule ./cache_as_ram_auto.inc
depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
end
end
##
## Build our 16 bit and 32 bit coreboot entry code
##
if CONFIG_USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/entry16.inc
ldscript /cpu/x86/16bit/entry16.lds
end
mainboardinit cpu/x86/32bit/entry32.inc
if CONFIG_USE_INIT
ldscript /cpu/x86/32bit/entry32.lds
end
if CONFIG_USE_INIT
ldscript /cpu/amd/car/cache_as_ram.lds
end
##
## Build our reset vector (This is where coreboot is entered)
##
if CONFIG_USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
mainboardinit cpu/x86/32bit/reset32.inc
ldscript /cpu/x86/32bit/reset32.lds
end
##
## Include an id string (For safe flashing)
##
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
##
## Setup Cache-As-Ram
##
mainboardinit cpu/amd/car/cache_as_ram.inc
###
### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
if CONFIG_USE_FALLBACK_IMAGE
ldscript /arch/i386/lib/failover.lds
end
###
### O.k. We aren't just an intermediary anymore!
###
##
## Setup RAM
##
if CONFIG_USE_INIT
initobject cache_as_ram_auto.o
else
mainboardinit ./cache_as_ram_auto.inc
end
##
## Include the secondary Configuration files
##
config chip.h
# sample config for amd/serengeti_cheetah
chip northbridge/amd/amdk8/root_complex
device apic_cluster 0 on
chip cpu/amd/socket_F
device apic 0 on end
end
end
device pci_domain 0 on
chip northbridge/amd/amdk8
device pci 18.0 on end
device pci 18.0 on end
device pci 18.0 on # northbridge
# devices on link 0
chip southbridge/broadcom/bcm5780 # HT2000
device pci 0.0 on end # PXB 1 0x0130
device pci 1.0 on # PXB 2 0x0130
device pci 4.0 on end # GB E 0x1668 vid = 0x14e4
device pci 4.1 on end # GB E 0x1669 vid = 0x14e4
end
device pci 2.0 on end # PCI E 1 #0x0132
device pci 3.0 on end # PCI E 2
device pci 4.0 on end # PCI E 3
device pci 5.0 on end # PCI E 4
end
chip southbridge/broadcom/bcm5785 # HT1000
device pci 0.0 on # HT PXB 0x0036
device pci d.0 on end # PPBX 0x0104
device pci e.0 on end # SATA 0x024a
device pci e.1 on end # SATA 0x024a bx_a001
device pci e.2 on end # SATA 0x024a bx_a001
device pci e.3 on end # SATA 0x024a bx_a001
end
device pci 1.0 on # Legacy pci main 0x0205
end
device pci 1.1 on end # IDE 0x0214
device pci 1.2 on # LPC 0x0234
chip superio/nsc/pc87417
device pnp 2e.0 off # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
device pnp 2e.1 off # Parallel Port
io 0x60 = 0x378
irq 0x70 = 7
end
device pnp 2e.2 off # Com 2
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.3 on # Com 1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.4 off end # SWC
device pnp 2e.5 off end # Mouse
device pnp 2e.6 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
end
device pnp 2e.7 off end # GPIO
device pnp 2e.f off end # XBUS
device pnp 2e.10 on #RTC
io 0x60 = 0x70
io 0x62 = 0x72
end
end
end
device pci 1.3 on end # WDTimer 0x0238
device pci 1.4 on end # XIOAPIC0 0x0235
device pci 1.5 on end # XIOAPIC1
device pci 1.6 on end # XIOAPIC2
device pci 2.0 on end # USB 0x0223
device pci 2.1 on end # USB
device pci 2.2 on end # USB
device pci 3.0 on end # it is in bcm5785_0 bus
end
end # device pci 18.0
device pci 18.1 on end
device pci 18.2 on end
device pci 18.3 on end
end # amdk8
end #pci_domain
# chip drivers/generic/debug
# device pnp 0.0 off end # chip name
# device pnp 0.1 on end # pci_regs_all
# device pnp 0.2 off end # mem
# device pnp 0.3 off end # cpuid
# device pnp 0.4 off end # smbus_regs_all
# device pnp 0.5 off end # dual core msr
# device pnp 0.6 off end # cache size
# device pnp 0.7 off end # tsc
# end
end
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