1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
|
chip soc/intel/alderlake
# FSP configuration
register "eist_enable" = "1"
# Sagv Configuration
register "sagv" = "SaGv_Enabled"
register "RMT" = "0"
register "enable_c6dram" = "1"
register "pmc_gpe0_dw0" = "GPP_J"
register "pmc_gpe0_dw1" = "GPP_VPGIO"
register "pmc_gpe0_dw2" = "GPD"
# USB Configuration
# TODO: Verify
register "usb2_ports[0]" = "USB2_PORT_MID(OC2)"
register "usb2_ports[1]" = "USB2_PORT_MID(OC1)"
register "usb2_ports[2]" = "USB2_PORT_MID(OC0)"
register "usb2_ports[3]" = "USB2_PORT_MID(OC0)"
register "usb2_ports[4]" = "USB2_PORT_MID(OC3)"
register "usb2_ports[5]" = "USB2_PORT_MID(OC3)"
register "usb2_ports[6]" = "USB2_PORT_MID(OC7)"
register "usb2_ports[7]" = "USB2_PORT_MID(OC0)"
register "usb2_ports[8]" = "USB2_PORT_MID(OC2)"
register "usb2_ports[9]" = "USB2_PORT_MID(OC7)"
register "usb2_ports[10]" = "USB2_PORT_MID(OC0)"
register "usb2_ports[11]" = "USB2_PORT_MID(OC0)"
register "usb2_ports[12]" = "USB2_PORT_MID(OC0)"
register "usb2_ports[13]" = "USB2_PORT_MID(OC6)"
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)"
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)"
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)"
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)"
register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC7)"
register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC7)"
register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC2)"
register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC2)"
register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC0)"
register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC0)"
# LPC generic I/O ranges
register "gen1_dec" = "0x00fc0201"
register "gen2_dec" = "0x003c0a01"
register "gen3_dec" = "0x000c03f1"
register "gen4_dec" = "0x000c0081"
register "sata_salp_support" = "1"
register "sata_ports_enable" = "{
[0] = 1,
[1] = 1,
[2] = 1,
[3] = 1,
[4] = 1,
[5] = 1,
[6] = 1,
[7] = 1,
}"
register "sata_ports_dev_slp" = "{
[0] = 0,
[1] = 0,
[2] = 0,
[3] = 0,
[4] = 0,
[5] = 0,
[6] = 1,
[7] = 1,
}"
device domain 0 on
device ref igpu on end
device ref crashlog off end
device ref xhci on end
device ref cnvi_wifi on end
device ref heci1 on end
device ref heci2 off end
device ref ide_r off end
device ref kt off end
device ref heci3 off end
device ref heci4 off end
device ref sata on end
device ref p2sb on end
device ref hda on end
device ref smbus on end
end
end
|
