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##
## This file is part of the coreboot project.
##
## Copyright (C) 2007 AMD
## (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
## Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de>
## (Thanks to LSRA University of Mannheim for their support)
## Copyright (C) 2008 Jonathan A. Kollasch <jakllsch@kollasch.net>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
## XIP_ROM_SIZE must be a power of 2.
default XIP_ROM_SIZE = 64 * 1024
include /config/failovercalculation.lb
arch i386 end
##
## Build the objects we have code for in this directory.
##
driver mainboard.o
#dir /drivers/ati/ragexl
# Needed by irq_tables and mptable and acpi_tables.
object get_bus_conf.o
if HAVE_MP_TABLE
object mptable.o
end
if HAVE_PIRQ_TABLE
object irq_tables.o
end
if CONFIG_USE_INIT
makerule ./auto.o
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@"
end
else
makerule ./auto.inc
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
end
end
##
## Build our 16 bit and 32 bit coreboot entry code.
##
if HAVE_FAILOVER_BOOT
if USE_FAILOVER_IMAGE
mainboardinit cpu/x86/16bit/entry16.inc
ldscript /cpu/x86/16bit/entry16.lds
end
else
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/entry16.inc
ldscript /cpu/x86/16bit/entry16.lds
end
end
mainboardinit cpu/x86/32bit/entry32.inc
if CONFIG_USE_INIT
ldscript /cpu/x86/32bit/entry32.lds
ldscript /cpu/amd/car/cache_as_ram.lds
end
##
## Build our reset vector (this is where coreboot is entered).
##
if HAVE_FAILOVER_BOOT
if USE_FAILOVER_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
mainboardinit cpu/x86/32bit/reset32.inc
ldscript /cpu/x86/32bit/reset32.lds
end
else
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
mainboardinit cpu/x86/32bit/reset32.inc
ldscript /cpu/x86/32bit/reset32.lds
end
end
##
## Include an ID string (for safe flashing).
##
mainboardinit southbridge/nvidia/ck804/id.inc
ldscript /southbridge/nvidia/ck804/id.lds
##
## ROMSTRAP table for CK804
##
if HAVE_FAILOVER_BOOT
if USE_FAILOVER_IMAGE
mainboardinit southbridge/nvidia/ck804/romstrap.inc
ldscript /southbridge/nvidia/ck804/romstrap.lds
end
else
if USE_FALLBACK_IMAGE
mainboardinit southbridge/nvidia/ck804/romstrap.inc
ldscript /southbridge/nvidia/ck804/romstrap.lds
end
end
##
## Setup Cache-As-Ram
##
mainboardinit cpu/amd/car/cache_as_ram.inc
###
### This is the early phase of coreboot startup.
### Things are delicate and we test to see if we should
### failover to another image.
###
if HAVE_FAILOVER_BOOT
if USE_FAILOVER_IMAGE
ldscript /arch/i386/lib/failover_failover.lds
end
else
if USE_FALLBACK_IMAGE
ldscript /arch/i386/lib/failover.lds
end
end
###
### O.k. We aren't just an intermediary anymore!
###
##
## Setup RAM
##
if CONFIG_USE_INIT
initobject auto.o
else
mainboardinit ./auto.inc
end
##
## Include the secondary configuration files
##
config chip.h
chip northbridge/amd/amdk8/root_complex # Root complex
device apic_cluster 0 on # APIC cluster
chip cpu/amd/socket_754 # Socket 754 CPU
device apic 0 on end # APIC
end
end
device pci_domain 0 on # PCI domain
chip northbridge/amd/amdk8 # mc0
device pci 18.0 on # Northbridge
# Devices on link 0, link 0 == LDT 0
chip southbridge/nvidia/ck804 # Southbridge
device pci 0.0 on end # HT
device pci 1.0 on # LPC
chip superio/winbond/w83627thf # Super I/O
device pnp 4e.0 on # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
device pnp 4e.1 on # Parallel port
io 0x60 = 0x378
irq 0x70 = 7
end
device pnp 4e.2 on # Com1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 4e.3 on # Com2
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 4e.5 on # PS/2 keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
irq 0x72 = 12
end
device pnp 4e.7 off end # Game, MIDI, GPIO 1, GPIO 5
device pnp 4e.8 off end # GPIO 2
device pnp 4e.9 off end # GPIO 3, GPIO 4
device pnp 4e.a off end # ACPI
device pnp 4e.b on # Hardware monitor
io 0x60 = 0x290
irq 0x70 = 0
end
end
end
device pci 1.1 on end # SMbus
device pci 2.0 on end # USB 1.1
device pci 2.1 on end # USB 2
device pci 4.0 on end # Onboard audio (ACI)
device pci 4.1 off end # Onboard modem (MCI) -- not wired out
device pci 6.0 on end # IDE
device pci 7.0 on end # SATA 1
device pci 8.0 on end # SATA 0
device pci 9.0 on end # PCI
device pci a.0 on end # NIC
device pci b.0 off end # PCI E 3 -- not wired out
device pci c.0 off end # PCI E 2 -- not wired out
device pci d.0 on end # PCI E 1
device pci e.0 on end # PCI E 0
register "ide0_enable" = "1"
register "ide1_enable" = "1"
register "sata0_enable" = "1"
register "sata1_enable" = "1"
# register "mac_eeprom_smbus" = "3"
# register "mac_eeprom_addr" = "0x51"
end
end
device pci 18.1 on end
device pci 18.2 on end
device pci 18.3 on end
end
end
end
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