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uses ISA_IO_BASE
uses CONFIG_CBFS
uses ISA_MEM_BASE
uses PCIC0_CFGADDR
uses PCIC0_CFGDATA
uses PNP_CFGADDR
uses PNP_CFGDATA
uses _IO_BASE
uses CROSS_COMPILE
uses HAVE_OPTION_TABLE
uses CONFIG_SANDPOINT_ALTIMUS
uses CONFIG_COMPRESS
uses DEFAULT_CONSOLE_LOGLEVEL
uses CONFIG_USE_INIT
uses CONFIG_CHIP_CONFIGURE
uses NO_POST
uses CONFIG_CONSOLE_SERIAL8250
uses TTYS0_BASE
uses CONFIG_IDE
uses CONFIG_FS_PAYLOAD
uses CONFIG_FS_EXT2
uses CONFIG_FS_ISO9660
uses CONFIG_FS_FAT
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
uses CONFIG_PRECOMPRESSED_PAYLOAD
uses AUTOBOOT_CMDLINE
uses PAYLOAD_SIZE
uses ROM_SIZE
uses ROM_IMAGE_SIZE
uses _RESET
uses _EXCEPTION_VECTORS
uses _ROMBASE
uses _ROMSTART
uses _RAMBASE
uses _RAMSTART
uses STACK_SIZE
uses HEAP_SIZE
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
uses COREBOOT_EXTRA_VERSION
uses CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
##
## Set memory map
##
default ISA_IO_BASE=0xfe000000
default ISA_MEM_BASE=0xfd000000
default PCIC0_CFGADDR=0xfec00000
default PCIC0_CFGDATA=0xfee00000
default PNP_CFGADDR=0x15c
default PNP_CFGDATA=0x15d
default _IO_BASE=ISA_IO_BASE
##
## The default compiler
##
default CC="$(CROSS_COMPILE)gcc"
default HOSTCC="gcc"
## use a cross compiler
#default CROSS_COMPILE="powerpc-eabi-"
#default CROSS_COMPILE="ppc_74xx-"
## Use stage 1 initialization code
default CONFIG_USE_INIT=1
## Use static configuration
default CONFIG_CHIP_CONFIGURE=1
## We don't use compressed image
default CONFIG_COMPRESS=0
## Turn off POST codes
default NO_POST=1
## Enable serial console
default DEFAULT_CONSOLE_LOGLEVEL=8
default CONFIG_CONSOLE_SERIAL8250=1
default TTYS0_BASE=0x3f8
## Load payload using filo
default CONFIG_IDE=1
default CONFIG_FS_PAYLOAD=1
default CONFIG_FS_EXT2=1
default CONFIG_FS_ISO9660=1
default CONFIG_FS_FAT=1
default AUTOBOOT_CMDLINE="hdc1:/vmlinuz"
# coreboot must fit into 128KB
default ROM_IMAGE_SIZE=131072
default ROM_SIZE={ROM_IMAGE_SIZE+PAYLOAD_SIZE}
default PAYLOAD_SIZE=262144
# Set stack and heap sizes (stage 2)
default STACK_SIZE=0x10000
default HEAP_SIZE=0x10000
# Sandpoint Demo Board
## Base of ROM
default _ROMBASE=0xfff00000
## Sandpoint reset vector
default _RESET=_ROMBASE+0x100
## Exception vectors (other than reset vector)
default _EXCEPTION_VECTORS=_RESET+0x100
## Start of coreboot in the boot rom
## = _RESET + exeception vector table size
default _ROMSTART=_RESET+0x3100
## Coreboot C code runs at this location in RAM
default _RAMBASE=0x00100000
default _RAMSTART=0x00100000
### End Options.lb
#
# CBFS
#
#
default CONFIG_CBFS=0
end
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