blob: 9a83bc96d8bebd3ac96e07ab0a5e22e5e85785e9 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
|
##
## This file is part of the coreboot project.
##
## Copyright (C) 2008 LiPPERT Embedded Computers GmbH
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
## Based on Options.lb from AMD's DB800 mainboard.
uses HAVE_MP_TABLE
uses HAVE_PIRQ_TABLE
uses USE_FALLBACK_IMAGE
uses HAVE_FALLBACK_BOOT
uses HAVE_HARD_RESET
uses HAVE_OPTION_TABLE
uses USE_OPTION_TABLE
uses CONFIG_ROM_PAYLOAD
uses CONFIG_IDE
uses CONFIG_FS_PAYLOAD
uses CONFIG_FS_EXT2
uses AUTOBOOT_DELAY
uses AUTOBOOT_CMDLINE
uses IRQ_SLOT_COUNT
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
uses COREBOOT_EXTRA_VERSION
uses ARCH
uses FALLBACK_SIZE
uses STACK_SIZE
uses HEAP_SIZE
uses ROM_SIZE
uses ROM_SECTION_SIZE
uses ROM_IMAGE_SIZE
uses ROM_SECTION_SIZE
uses ROM_SECTION_OFFSET
uses CONFIG_ROM_PAYLOAD_START
uses CONFIG_COMPRESS
uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
uses CONFIG_PRECOMPRESSED_PAYLOAD
uses PAYLOAD_SIZE
uses _ROMBASE
uses _RAMBASE
uses XIP_ROM_SIZE
uses XIP_ROM_BASE
uses HAVE_MP_TABLE
uses CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
uses DEBUG
uses DEFAULT_CONSOLE_LOGLEVEL
uses MAXIMUM_CONSOLE_LOGLEVEL
uses CONFIG_CONSOLE_SERIAL8250
uses TTYS0_BAUD
uses TTYS0_BASE
uses TTYS0_LCS
uses CONFIG_UDELAY_TSC
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses CONFIG_VIDEO_MB
uses USE_DCACHE_RAM
uses DCACHE_RAM_BASE
uses DCACHE_RAM_SIZE
uses PIRQ_ROUTE
## ROM_SIZE is the size of boot ROM that this board will use.
default ROM_SIZE = 512*1024
###
### Build options
###
default CONFIG_CONSOLE_VGA = 0
default CONFIG_VIDEO_MB = 8
default CONFIG_PCI_ROM_RUN = 0
##
## Build code for the fallback boot
##
default HAVE_FALLBACK_BOOT = 1
##
## no MP table
##
default HAVE_MP_TABLE = 0
##
## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET = 0
## Delay timer options
##
default CONFIG_UDELAY_TSC = 1
default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
##
## Build code to export a programmable irq routing table
##
default HAVE_PIRQ_TABLE = 1
default IRQ_SLOT_COUNT = 7
default PIRQ_ROUTE = 1
##
## Build code to export a CMOS option table
##
default HAVE_OPTION_TABLE = 0
###
### coreboot layout values
###
## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 64 * 1024
default FALLBACK_SIZE = 128 * 1024
##
## enable CACHE_AS_RAM specifics
##
default USE_DCACHE_RAM = 1
default DCACHE_RAM_BASE = 0xc8000
default DCACHE_RAM_SIZE = 0x08000
##
## Use a small 8K stack
##
default STACK_SIZE = 0x2000
##
## Use a small 16K heap
##
default HEAP_SIZE = 0x4000
##
## Only use the option table in a normal image
##
#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
default USE_OPTION_TABLE = 0
default _RAMBASE = 0x00004000
default CONFIG_ROM_PAYLOAD = 1
##
## The default compiler
##
default CROSS_COMPILE = ""
default CC = "$(CROSS_COMPILE)gcc -m32"
default HOSTCC = "gcc"
##
## The Serial Console
##
# To Enable the Serial Console
default CONFIG_CONSOLE_SERIAL8250 = 1
## Select the serial console baud rate
default TTYS0_BAUD = 115200
#default TTYS0_BAUD = 57600
#default TTYS0_BAUD = 38400
#default TTYS0_BAUD = 19200
#default TTYS0_BAUD = 9600
#default TTYS0_BAUD = 4800
#default TTYS0_BAUD = 2400
#default TTYS0_BAUD = 1200
# Select the serial console base port
default TTYS0_BASE = 0x3f8
# Select the serial protocol
# This defaults to 8 data bits, 1 stop bit, and no parity
default TTYS0_LCS = 0x3
# Compile extra debugging code
default DEBUG = 1
##
### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately
## CRIT 3 critical conditions
## ERR 4 error conditions
## WARNING 5 warning conditions
## NOTICE 6 normal but significant condition
## INFO 7 informational
## DEBUG 8 debug-level messages
## SPEW 9 Way too many details
## Request this level of debugging output
default DEFAULT_CONSOLE_LOGLEVEL = 8
## At a maximum only compile in this level of debugging
default MAXIMUM_CONSOLE_LOGLEVEL = 8
end
|
