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chip northbridge/intel/sandybridge
# IGD Displays
register "gfx" = "GMA_STATIC_DISPLAYS(1)"
# Enable DisplayPort Hotplug with 6ms pulse
register "gpu_dp_d_hotplug" = "0x06"
# Enable Panel as LVDS and configure power delays
register "gpu_panel_port_select" = "PANEL_PORT_LVDS"
register "gpu_panel_power_cycle_delay" = "5"
register "gpu_panel_power_up_delay" = "300" # T1+T2: 30ms
register "gpu_panel_power_down_delay" = "300" # T5+T6: 30ms
register "gpu_panel_power_backlight_on_delay" = "2000" # T3: 200ms
register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms
register "gpu_cpu_backlight" = "0x1155"
register "gpu_pch_backlight" = "0x06100610"
register "spd_addresses" = "{0x50, 0, 0x51, 0}"
register "ec_present" = "1" # I have an embedded controller
register "max_mem_clock_mhz" = "666" # So DDR3 freq = 1333
register "usb_port_config" = "{
{ 1, 0, 0x0040 },
{ 1, 1, 0x0080 },
{ 1, 3, 0x0080 },
{ 1, 3, 0x0080 },
{ 1, 0, 0x0080 },
{ 1, 0, 0x0080 },
{ 1, 2, 0x0040 },
{ 1, 2, 0x0040 },
{ 1, 6, 0x0080 },
{ 1, 5, 0x0080 },
{ 1, 6, 0x0080 },
{ 1, 6, 0x0080 },
{ 1, 7, 0x0080 },
{ 1, 6, 0x0080 },}"
chip cpu/intel/model_206ax
# Values obtained from vendor BIOS v1.46
# schematics say 33Amps for 17W TDP, 53Amps for 35W TDP
register "pp0_current_limit" = "98"
# schematics say 33Amps for GFX
register "pp1_current_limit" = "33"
register "pp0_psi[VR12_PSI1]" = "{VR12_2_PHASES, 20}"
register "pp0_psi[VR12_PSI2]" = "{VR12_ALL_PHASES, 5}"
register "pp0_psi[VR12_PSI3]" = "{VR12_ALL_PHASES, 1}"
register "pp1_psi[VR12_PSI1]" = "{VR12_2_PHASES, 20}"
register "pp1_psi[VR12_PSI2]" = "{VR12_ALL_PHASES, 5}"
register "pp1_psi[VR12_PSI3]" = "{VR12_ALL_PHASES, 1}"
device cpu_cluster 0 on end
end
device domain 0 on
subsystemid 0x17aa 0x21db inherit
device ref host_bridge on end
device ref peg10 off end
device ref igd on end
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
# GPI routing
# 0 No effect (default)
# 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
# 2 SCI (if corresponding GPIO_EN bit is also set)
register "alt_gp_smi_en" = "0x0000"
register "gpi1_routing" = "2"
register "gpi13_routing" = "2"
# Enable SATA ports 0 (HDD bay) & 1 (dock) & 2 (msata)
register "sata_port_map" = "0x7"
# Set max SATA speed to 6.0 Gb/s
register "sata_interface_speed_support" = "0x3"
register "gen1_dec" = "0x7c1601"
register "gen2_dec" = "0x0c15e1"
register "gen4_dec" = "0x0c06a1"
register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }"
# Enable zero-based linear PCIe root port functions
register "pcie_port_coalesce" = "true"
register "spi_uvscc" = "0x2005"
register "spi_lvscc" = "0x2005"
device ref mei1 on end
device ref mei2 off end
device ref me_ide_r off end
device ref me_kt off end
device ref gbe on
subsystemid 0x17aa 0x21ce
end
device ref ehci2 on end
device ref hda on end
device ref pcie_rp1 off end
device ref pcie_rp2 on
smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthShort"
"WIFI" "SlotDataBusWidth1X"
end
device ref pcie_rp3 off end
device ref pcie_rp4 on
smbios_slot_desc "7" "3" "ExpressCard Slot" "8"
end
device ref pcie_rp5 on
chip drivers/ricoh/rce822
register "sdwppol" = "1"
register "disable_mask" = "0x87"
device pci 00.0 on end
end
end
device ref pcie_rp6 off end
device ref pcie_rp7 on end # Optional XHCI controller
device ref pcie_rp8 off end
device ref ehci1 on end
device ref pci_bridge off end
device ref lpc on
chip ec/lenovo/pmh7
device pnp ff.1 on end # dummy
register "backlight_enable" = "true"
register "dock_event_enable" = "true"
end
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end
chip ec/lenovo/h8
device pnp ff.2 on # dummy
io 0x60 = 0x62
io 0x62 = 0x66
io 0x64 = 0x1600
io 0x66 = 0x1604
end
register "config0" = "0xa6"
register "config1" = "0x01"
register "config2" = "0xa0"
register "config3" = "0x60"
register "has_keyboard_backlight" = "0"
register "beepmask0" = "0x00"
register "beepmask1" = "0x86"
register "has_power_management_beeps" = "1"
register "event2_enable" = "0xff"
register "event3_enable" = "0xff"
register "event4_enable" = "0xd0"
register "event5_enable" = "0xfc"
register "event6_enable" = "0x00"
register "event7_enable" = "0x81"
register "event8_enable" = "0x7b"
register "event9_enable" = "0xff"
register "eventc_enable" = "0xff"
register "eventd_enable" = "0xff"
register "evente_enable" = "0x0d"
# BDC detection is broken on this board:
# BDC shorts pin14 and pin1
# BDC's connector pin14 is left floating
# BDC's connector pin1 is routed to SB GPIO 54
register "has_bdc_detection" = "0"
register "has_wwan_detection" = "1"
register "wwan_gpio_num" = "70"
register "wwan_gpio_lvl" = "0"
end
end
device ref sata1 on end
device ref smbus on
# eeprom, 8 virtual devices, same chip
chip drivers/i2c/at24rf08c
device i2c 54 on end
device i2c 55 on end
device i2c 56 on end
device i2c 57 on end
device i2c 5c on end
device i2c 5d on end
device i2c 5e on end
device i2c 5f on end
end
end
device ref sata2 off end
device ref thermal on end
end
end
end
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