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FLASH@0xff800000 0x800000 {
SI_ALL@0x0 0x500000 {
SI_DESC@0x0 0x1000
SI_GBE@0x1000 0x2000
SI_ME@0x3000 0x4ed000
}
SI_BIOS@0x500000 0x300000 {
RW_SECTION_A 0x180000 {
VBLOCK_A 0x10000
FW_MAIN_A(CBFS)
RW_FWID_A 0x40
}
UNIFIED_MRC_CACHE 0x20000 {
RECOVERY_MRC_CACHE 0x10000
RW_MRC_CACHE 0x10000
}
RW_VPD(PRESERVE) 0x1000
SMMSTORE(PRESERVE) 0x40000
RW_NVRAM(PRESERVE) 0x2000
WP_RO {
RO_VPD(PRESERVE) 0x1000
RO_SECTION 0x11e000 {
FMAP 0x800
RO_FRID 0x40
RO_PADDING 0x7c0
GBB 0x1e000
COREBOOT(CBFS)
}
}
}
}
|
