blob: 6505d139c174e2d43bfc4bc0ba7ac50fd967afc2 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
|
chip northbridge/intel/sandybridge
register "gfx" = "GMA_STATIC_DISPLAYS(0)"
register "gpu_cpu_backlight" = "0x00000000"
register "gpu_dp_b_hotplug" = "0"
register "gpu_dp_c_hotplug" = "0"
register "gpu_dp_d_hotplug" = "0"
register "gpu_panel_port_select" = "PANEL_PORT_LVDS"
register "gpu_panel_power_backlight_off_delay" = "0"
register "gpu_panel_power_backlight_on_delay" = "0"
register "gpu_panel_power_cycle_delay" = "0"
register "gpu_panel_power_down_delay" = "0"
register "gpu_panel_power_up_delay" = "0"
register "gpu_pch_backlight" = "0x00000000"
device cpu_cluster 0 on
chip cpu/intel/model_206ax
register "acpi_c1" = "1"
register "acpi_c2" = "3"
register "acpi_c3" = "5"
device lapic 0x0 on end
device lapic 0xacac off end
end
end
device domain 0 on
subsystemid 0x17aa 0x21dd inherit
device pci 00.0 on end # Host bridge
device pci 01.0 on end # PCIe Bridge for discrete graphics
device pci 02.0 on end # Internal graphics VGA controller
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
register "c2_latency" = "0x0065"
register "docking_supported" = "1"
register "gen1_dec" = "0x007c1611"
register "gen2_dec" = "0x00040069"
register "gen3_dec" = "0x000c0701"
register "gen4_dec" = "0x00000000"
register "gpi13_routing" = "2"
register "gpi6_routing" = "2"
register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 1, 0, 0, 0 }"
register "pcie_port_coalesce" = "1"
register "sata_interface_speed_support" = "0x3"
register "sata_port_map" = "0x3b"
register "spi_uvscc" = "0"
register "spi_lvscc" = "0x2005"
device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R
device pci 16.3 off end # Management Engine KT
device pci 19.0 off end # Intel Gigabit Ethernet
device pci 1a.0 on end # USB2 EHCI #2
device pci 1b.0 on end # High Definition Audio Audio controller
device pci 1c.0 on end # PCIe Port #1
device pci 1c.1 on end # PCIe Port #2
device pci 1c.2 on end # PCIe Port #3
device pci 1c.3 on end # PCIe Port #4
device pci 1c.4 on end # PCIe Port #5
device pci 1c.5 on end # PCIe Port #6
device pci 1c.6 off end # PCIe Port #7
device pci 1c.7 off end # PCIe Port #8
device pci 1d.0 on end # USB2 EHCI #1
device pci 1e.0 off end # PCI bridge
device pci 1f.0 on # LPC bridge PCI-LPC bridge
chip ec/lenovo/pmh7
register "backlight_enable" = "0x01"
register "dock_event_enable" = "0x01"
device pnp ff.1 on end # dummy
end
chip ec/lenovo/h8
register "config0" = "0xa7"
register "config1" = "0x09"
register "config2" = "0xa0"
register "config3" = "0xc2"
register "beepmask0" = "0x00"
register "beepmask1" = "0x86"
register "has_power_management_beeps" = "0"
register "event2_enable" = "0xff"
register "event3_enable" = "0xff"
register "event4_enable" = "0xff"
register "event5_enable" = "0xff"
register "event6_enable" = "0xff"
register "event7_enable" = "0xff"
register "event8_enable" = "0xff"
register "event9_enable" = "0xff"
register "eventa_enable" = "0xff"
register "eventb_enable" = "0xff"
register "eventc_enable" = "0xff"
register "eventd_enable" = "0xff"
register "evente_enable" = "0xff"
device pnp ff.2 on # dummy
io 0x60 = 0x62
io 0x62 = 0x66
io 0x64 = 0x1600
io 0x66 = 0x1604
end
end
end # LPC bridge
device pci 1f.2 on end # SATA Controller 1
device pci 1f.3 on # SMBus
chip drivers/i2c/at24rf08c # eeprom, 8 virtual devices, same chip
device i2c 54 on end
device i2c 55 on end
device i2c 56 on end
device i2c 57 on end
device i2c 5c on end
device i2c 5d on end
device i2c 5e on end
device i2c 5f on end
end
end # SMBus
device pci 1f.5 off end # SATA Controller 2
device pci 1f.6 off end # Thermal
end
end
end
|
