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# SPDX-License-Identifier: GPL-2.0-only
chip soc/intel/skylake
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
}"
register "PmConfigSlpS3MinAssert" = "SLP_S3_MIN_ASSERT_50MS"
register "PmConfigSlpS4MinAssert" = "SLP_S4_MIN_ASSERT_4S"
register "PmConfigSlpSusMinAssert" = "SLP_SUS_MIN_ASSERT_4S"
register "PmConfigSlpAMinAssert" = "SLP_A_MIN_ASSERT_2S"
register "PmConfigPciClockRun" = "1"
register "PmConfigPwrCycDur" = "RESET_POWER_CYCLE_4S"
# VR Settings Configuration for 2 Domains
#+----------------+-------+-------+
#| Domain/Setting | VCC | VCCGT |
#+----------------+-------+-------+
#| Psi1Threshold | 20A | 20A |
#| Psi2Threshold | 5A | 5A |
#| Psi3Threshold | 1A | 1A |
#| Psi3Enable | 1 | 1 |
#| Psi4Enable | 1 | 1 |
#| ImonSlope | 0 | 0 |
#| ImonOffset | 0 | 0 |
#| IccMax | 55A | 35A |
#| VrVoltageLimit | 1.52V | 1.52V |
#| AcLoadline | 2.1 | 3.1 |
#| DcLoadline | 2.1 | 3.1 |
#+----------------+-------+-------+
register "domain_vr_config[VR_IA_CORE]" = "{
.vr_config_enable = 1,
.psi1threshold = VR_CFG_AMP(20),
.psi2threshold = VR_CFG_AMP(5),
.psi3threshold = VR_CFG_AMP(1),
.psi3enable = 1,
.psi4enable = 1,
.imon_slope = 0x0,
.imon_offset = 0x0,
.icc_max = VR_CFG_AMP(55),
.voltage_limit = 1520,
.ac_loadline = 210,
.dc_loadline = 210,
}"
register "domain_vr_config[VR_GT_UNSLICED]" = "{
.vr_config_enable = 1,
.psi1threshold = VR_CFG_AMP(20),
.psi2threshold = VR_CFG_AMP(5),
.psi3threshold = VR_CFG_AMP(1),
.psi3enable = 1,
.psi4enable = 1,
.imon_slope = 0x0,
.imon_offset = 0x0,
.icc_max = VR_CFG_AMP(35),
.voltage_limit = 1520,
.ac_loadline = 310,
.dc_loadline = 310,
}"
# Vendor set Psys Pmax to 30W
register "power_limits_config" = "{
.psys_pmax = 30,
}"
# TODO
# Send an extra VR mailbox command for the PS4 exit issue
register "SendVrMbxCmd" = "2"
device cpu_cluster 0 on
device lapic 0 on end
end
device domain 0 on
device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device
device pci 08.0 on end # Gaussian Mixture Model
device pci 14.0 on # USB xHCI
register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)"
register "usb2_ports[1]" = "USB2_PORT_LONG(OC0)"
register "usb2_ports[2]" = "USB2_PORT_LONG(OC1)"
register "usb2_ports[3]" = "USB2_PORT_LONG(OC1)"
register "usb2_ports[4]" = "USB2_PORT_LONG(OC2)" # Debug
end
device pci 14.1 off end # USB xDCI (OTG)
device pci 14.2 on end # Thermal Subsystem
device pci 15.0 off end # I2C #0
device pci 15.1 off end # I2C #1
device pci 15.2 off end # I2C #2
device pci 15.3 off end # I2C #3
device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R
device pci 16.3 off end # Management Engine KT Redirection
device pci 16.4 off end # Management Engine Interface 3
device pci 17.0 on # SATA
register "SataSalpSupport" = "1"
register "SataPortsEnable[0]" = "1"
register "SataPortsEnable[1]" = "1"
register "SataPortsEnable[2]" = "1"
# SataPortsDevSlp not supported
end
device pci 19.0 off end # UART #2
device pci 1c.4 off end # PCI Express Port 5
device pci 1c.5 off end # PCI Express Port 6
device pci 1c.6 off end # PCI Express Port 7
device pci 1c.7 off end # PCI Express Port 8
device pci 1d.0 on # PCI Express Port 9 (COMe 0)
register "PcieRpEnable[8]" = "1"
end
device pci 1d.1 on # PCI Express Port 10 (COMe 1)
register "PcieRpEnable[9]" = "1"
end
device pci 1d.2 on # PCI Express Port 11 (COMe 2)
register "PcieRpEnable[10]" = "1"
end
device pci 1e.0 off end # UART #0
device pci 1e.1 off end # UART #1
device pci 1e.2 off end # GSPI #0
device pci 1e.3 off end # GSPI #1
device pci 1f.0 on # LPC Interface
register "serirq_mode" = "SERIRQ_CONTINUOUS"
# EC/kempld at 0xa80/0xa81
register "gen1_dec" = "0x00000a81"
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end
chip ec/kontron/kempld
register "uart[0]" = "{ KEMPLD_UART_3F8, 4 }"
device generic 0.0 on end # UART #0
end
end
device pci 1f.1 on end # P2SB
device pci 1f.2 on end # Power Management Controller
device pci 1f.3 off end # Intel HDA
device pci 1f.4 on # SMBus
chip drivers/i2c/nct7802y
device i2c 0x2e on end
end
end
device pci 1f.5 on end # PCH SPI
device pci 1f.6 on end # GbE
end
end
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