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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
DefinitionBlock(
"dsdt.aml",
"DSDT",
0x02, // DSDT revision: ACPI v2.0
"COREv2", // OEM id
"COREBOOT", // OEM table id
0x20090419 // OEM revision
)
{
// Some generic macros
Include ("acpi/platform.asl")
// global NVS and variables
Include ("../../../southbridge/intel/i82801gx/acpi/globalnvs.asl")
// General Purpose Events
//include ("acpi/gpe.asl")
//include ("acpi/thermal.asl")
Scope (\_SB) {
Device (PCI0)
{
Include ("../../../northbridge/intel/i945/acpi/i945.asl")
include ("../../../southbridge/intel/i82801gx/acpi/ich7.asl")
}
}
/* Chipset specific sleep states */
include ("../../../southbridge/intel/i82801gx/acpi/sleepstates.asl")
}
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