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##
## This file is part of the coreboot project.
##
##
## SPDX-License-Identifier: GPL-2.0-only
if BOARD_INTEL_SKLSDLBRK
config BOARD_SPECIFIC_OPTIONS
def_bool y
select BOARD_ROMSIZE_KB_4096
select CONSOLE_SERIAL
select DRIVERS_UART
select GENERIC_SPD_BIN
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select HAVE_OPTION_TABLE
select SKYLAKE_SOC_PCH_H
select SOC_INTEL_SKYLAKE
select SUPERIO_NUVOTON_NCT6776
select SUPERIO_NUVOTON_NCT6776_COM_A
select HAVE_CMOS_DEFAULT
select MAINBOARD_USES_IFD_GBE_REGION
config IRQ_SLOT_COUNT
int
default 18
config MAINBOARD_DIR
string
default "intel/saddlebrook"
config MAINBOARD_PART_NUMBER
string
default "Skylake Saddle Brook"
config MAINBOARD_FAMILY
string
default "Intel_SaddleBrook"
config MAX_CPUS
int
default 8
config TPM_PIRQ
hex
default 0x18 # GPP_E0_IRQ
endif
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