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##
## This file is part of the coreboot project.
##
## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
if BOARD_INTEL_MOHONPEAK
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select CPU_INTEL_SOCKET_RPGA989
select NORTHBRIDGE_INTEL_FSP_RANGELEY
select SOUTHBRIDGE_INTEL_FSP_RANGELEY
select BOARD_ROMSIZE_KB_2048 #actual chip is 8MB
select HAVE_ACPI_TABLES
select HAVE_OPTION_TABLE
select MMCONF_SUPPORT
select POST_IO
select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT
config MAINBOARD_DIR
string
default intel/mohonpeak
config MAINBOARD_PART_NUMBER
string
default "Mohon Peak CRB"
config MAX_CPUS
int
default 16
config CACHE_ROM_SIZE_OVERRIDE
hex
default 0x800000
config FSP_FILE
string
default "../intel/fsp/rangeley/FvFsp.bin"
config CBFS_SIZE
hex
default 0x00200000
config ENABLE_FSP_FAST_BOOT
bool
depends on HAVE_FSP_BIN
default y
config VIRTUAL_ROM_SIZE
hex
depends on ENABLE_FSP_FAST_BOOT
default 0x400000
config FSP_PACKAGE_DEFAULT
bool "Configure defaults for the Intel FSP package"
default n
config UART_FOR_CONSOLE
int
default 1
help
The Mohon Peak board uses COM2 (2f8) for the serial console.
config PAYLOAD_CONFIGFILE
string
default "$(top)/src/mainboard/$(MAINBOARDDIR)/config_seabios"
help
The Avoton/Rangeley chip does not allow devices to write into the 0xe000
segment. This means that USB/SATA devices will not work in SeaBIOS unless
we put the SeaBIOS buffer area down in the 0x9000 segment.
endif # BOARD_INTEL_MOHONPEAK
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