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##
## This file is part of the coreboot project.
##
## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
## Copyright (C) 2014 Intel Corporation
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
chip soc/intel/fsp_baytrail
#### ACPI Register Settings ####
register "fadt_pm_profile" = "PM_UNSPECIFIED"
register "fadt_boot_arch" = "ACPI_FADT_LEGACY_FREE"
#### FSP register settings ####
register "PcdSataMode" = "SATA_MODE_AHCI"
register "PcdMrcInitSPDAddr1" = "SPD_ADDR_DEFAULT"
register "PcdMrcInitSPDAddr2" = "SPD_ADDR_DEFAULT"
register "PcdMrcInitMmioSize" = "MMIO_SIZE_DEFAULT"
register "PcdeMMCBootMode" = "EMMC_FOLLOWS_DEVICETREE"
register "PcdIgdDvmt50PreAlloc" = "IGD_MEMSIZE_DEFAULT"
register "PcdApertureSize" = "APERTURE_SIZE_DEFAULT"
register "PcdGttSize" = "GTT_SIZE_DEFAULT"
register "PcdLpssSioEnablePciMode" = "LPSS_PCI_MODE_DEFAULT"
register "AzaliaAutoEnable" = "AZALIA_FOLLOWS_DEVICETREE"
register "LpeAcpiModeEnable" = "LPE_ACPI_MODE_DISABLED"
register "IgdRenderStandby" = "IGD_RENDER_STANDBY_ENABLE"
register "EnableMemoryDown" = "MEMORY_DOWN_ENABLE"
register "DRAMSpeed" = "DRAM_SPEED_1066MHZ"
register "DRAMType" = "DRAM_TYPE_DDR3L"
register "DIMM0Enable" = "DIMM0_ENABLE"
register "DIMM1Enable" = "DIMM1_DISABLE"
register "DIMMDWidth" = "DIMM_DWIDTH_X16"
register "DIMMDensity" = "DIMM_DENSITY_2G_BIT" # Setting for 1GB board - modified runtime for 2GB board in romstage.c to DIMM_DENSITY_4G_BIT
register "DIMMBusWidth" = "DIMM_BUS_WIDTH_64BIT"
register "DIMMSides" = "DIMM_SIDES_1RANK"
register "DIMMtCL" = "11"
register "DIMMtRPtRCD" = "11"
register "DIMMtWR" = "12"
register "DIMMtWTR" = "6"
register "DIMMtRRD" = "6"
register "DIMMtRTP" = "6"
register "DIMMtFAW" = "20"
device cpu_cluster 0 on
device lapic 0 on end
end
device domain 0 on
device pci 00.0 on end # 8086 0F00 - SoC router -
device pci 02.0 on end # 8086 0F31 - GFX micro HDMI
device pci 03.0 off end # 8086 0F38 - MIPI -
device pci 10.0 off end # 8086 0F14 - EMMC Port -
device pci 11.0 off end # 8086 0F15 - SDIO Port -
device pci 12.0 on end # 8086 0F16 - SD Port MicroSD on SD3
device pci 13.0 on end # 8086 0F23 - SATA AHCI Onboard & HSEC
device pci 14.0 on end # 8086 0F35 - USB XHCI - Onboard & HSEC - Enabling both EHCI and XHCI will default to EHCI if not changed at runtime
device pci 15.0 on end # 8086 0F28 - LP Engine Audio LSEC
device pci 17.0 off end # 8086 0F50 - MMC Port -
device pci 18.0 on end # 8086 0F40 - SIO - DMA -
device pci 18.1 off end # 8086 0F41 - I2C Port 1 (0) -
device pci 18.2 on end # 8086 0F42 - I2C Port 2 (1) - (testpoints)
device pci 18.3 off end # 8086 0F43 - I2C Port 3 (2) -
device pci 18.4 off end # 8086 0F44 - I2C Port 4 (3) -
device pci 18.5 off end # 8086 0F45 - I2C Port 5 (4) -
device pci 18.6 on end # 8086 0F46 - I2C Port 6 (5) LSEC
device pci 18.7 on end # 8086 0F47 - I2C Port 7 (6) HSEC
device pci 1a.0 on end # 8086 0F18 - TXE -
device pci 1b.0 off end # 8086 0F04 - HD Audio -
device pci 1c.0 on end # 8086 0F48 - PCIe Port 1 (0) -
device pci 1c.1 off end # 8086 0F4A - PCIe Port 2 (1) -
device pci 1c.2 on end # 8086 0F4C - PCIe Port 3 (2) Onboard GBE
device pci 1c.3 on end # 8086 0F4E - PCIe Port 4 (3) HSEC
device pci 1d.0 on end # 8086 0F34 - USB EHCI - Enabling both EHCI and XHCI will default to EHCI if not changed at runtime
device pci 1e.0 on end # 8086 0F06 - SIO - DMA -
device pci 1e.1 on end # 8086 0F08 - PWM 1 LSEC
device pci 1e.2 on end # 8086 0F09 - PWM 2 LSEC
device pci 1e.3 on end # 8086 0F0A - HSUART 1 LSEC
device pci 1e.4 on end # 8086 0F0C - HSUART 2 LSEC
device pci 1e.5 on end # 8086 0F0E - SPI LSEC
device pci 1f.0 on end # 8086 0F1C - LPC bridge No connector
device pci 1f.3 on end # 8086 0F12 - SMBus 0 SPC
end
end
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