blob: 636972f6042361c1523470916e3ea4f4be0fa88e (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
|
##
## This file is part of the coreboot project.
##
## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
## Copyright (C) 2014 Intel Corporation
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc.
##
if BOARD_INTEL_MINNOWMAX
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select SOC_INTEL_FSP_BAYTRAIL
select BOARD_ROMSIZE_KB_8192
select HAVE_ACPI_TABLES
select HAVE_OPTION_TABLE
select TSC_MONOTONIC_TIMER
select HAVE_ACPI_RESUME
config MAINBOARD_DIR
string
default "intel/minnowmax"
config MAINBOARD_PART_NUMBER
string
default "Minnow Max"
config MAX_CPUS
int
default 16
config CACHE_ROM_SIZE_OVERRIDE
hex
default 0x800000
config FSP_FILE
string
default "../intel/fsp/baytrail/BAYTRAIL_FSP.fd"
config MRC_CACHE_LOC
hex
default 0xfff80000
depends on ENABLE_FSP_FAST_BOOT
config CBFS_SIZE
hex
default 0x00300000
config ENABLE_FSP_FAST_BOOT
bool
depends on HAVE_FSP_BIN
default y
config VIRTUAL_ROM_SIZE
hex
depends on ENABLE_FSP_FAST_BOOT
default 0x800000
config POST_IO
bool
default n
config POST_DEVICE
bool
default n
config VGA_BIOS
bool
default y if FSP_PACKAGE_DEFAULT
endif # BOARD_INTEL_MINNOWMAX
|