blob: ec56e2665a0e79099b0f9c1afe95c1073fd5d15c (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
|
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
DefinitionBlock(
"dsdt.aml",
"DSDT",
0x02, // DSDT revision: ACPI v2.0
"COREv4", // OEM id
"COREBOOT", // OEM table id
0x20110725 // OEM revision
)
{
// Include mainboard configuration
#include <acpi/mainboard.asl>
// Include debug methods
#include <arch/x86/acpi/debug.asl>
// Some generic macros
#include "acpi/platform.asl"
// global NVS and variables
#include <southbridge/intel/fsp_rangeley/acpi/globalnvs.asl>
#include "acpi/thermal.asl"
#include <cpu/intel/fsp_model_406dx/acpi/cpu.asl>
Scope (\_SB) {
Device (PCI0)
{
#include <northbridge/intel/fsp_rangeley/acpi/rangeley.asl>
#include <southbridge/intel/fsp_rangeley/acpi/soc.asl>
}
}
/* Chipset specific sleep states */
#include <southbridge/intel/fsp_rangeley/acpi/sleepstates.asl>
}
|
