1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
|
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
* Copyright (C) 2015 Intel Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
* GNU General Public License for more details.
*/
#ifndef MAINBOARD_GPIO_H
#define MAINBOARD_GPIO_H
#include <soc/gpe.h>
#include <soc/gpio.h>
/* EC in RW */
#define GPIO_EC_IN_RW GPP_C6
/* BIOS Flash Write Protect */
#define GPIO_PCH_WP GPP_C23
/* Memory configuration board straps */
#define GPIO_MEM_CONFIG_0 GPP_C12
#define GPIO_MEM_CONFIG_1 GPP_C13
#define GPIO_MEM_CONFIG_2 GPP_C14
#define GPIO_MEM_CONFIG_3 GPP_C15
/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
#define GPE_EC_WAKE GPE0_LAN_WAK
/* GPP_B16 is WLAN_WAKE. GPP_B group is routed to DW0 in the GPE0 block */
#define GPE_WLAN_WAKE GPE0_DW0_16
/* Input device interrupt configuration */
#define TOUCHPAD_INT_L GPP_B3_IRQ
#define TOUCHSCREEN_INT_L GPP_E7_IRQ
#define MIC_INT_L GPP_F10_IRQ
/* GPP_E16 is EC_SCI_L. GPP_E group is routed to DW2 in the GPE0 block */
#define EC_SCI_GPI GPE0_DW2_16
#define EC_SMI_GPI GPP_E15
#ifndef __ACPI__
/* Pad configuration in ramstage. */
static const struct pad_config gpio_table[] = {
/* EC_PCH_RCIN */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1),
/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1),
/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1),
/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1),
/* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
/* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
/* PIRQA# */ /* GPP_A7 */
/* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
/* EC_LPC_CLK */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),
/* PCH_LPC_CLK */ /* GPP_A10 */
/* EC_HID_INT */ /* GPP_A11 */
/* ISH_KB_PROX_INT */ PAD_CFG_GPO(GPP_A12, 0, DEEP),
/* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
/* PM_SUS_STAT */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
/* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
/* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
/* SD_PWR_EN */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),
/* ACCEL INTERRUPT */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
/* ISH_GP1 */ /* GPP_A19 */
/* GYRO_DRDY */ PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1),
/* FLIP_ACCEL_INT */ PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1),
/* GYRO_INT */ PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1),
/* ISH_GP5 */ /* GPP_A23 */
/* CORE_VID0 */ /* GPP_B0 */
/* CORE_VID1 */ /* GPP_B1 */
/* HSJ_MIC_DET */ PAD_CFG_GPI(GPP_B2, NONE, DEEP),
/* TRACKPAD_INT */ PAD_CFG_GPI_APIC(GPP_B3, NONE, DEEP),
/* BT_RF_KILL */ PAD_CFG_GPO(GPP_B4, 0, DEEP),
/* SRCCLKREQ0# */ /* GPP_B5 */
/* WIFI_CLK_REQ */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
/* KEPLR_CLK_REQ */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
/* SRCCLKREQ3# */ /* GPP_B8 */
/* SSD_CLK_REQ */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
/* SRCCLKREQ5# */ /* GPP_B10 */
/* MPHY_EXT_PWR_GATE */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
/* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
/* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
/* GPP_B_14_SPKR */ PAD_CFG_GPI(GPP_B14, NONE, DEEP),
/* GSPI0_CS# */ /* GPP_B15 */
/* WLAN_PCIE_WAKE */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES),
/* SSD_PCIE_WAKE */ PAD_CFG_GPI(GPP_B17, NONE, DEEP),
/* GSPI0_MOSI */ /* GPP_B18 */
/* CCODEC_SPI_CS */ PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),
/* CODEC_SPI_CLK */ PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1),
/* CODEC_SPI_MISO */ PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1),
/* CODEC_SPI_MOSI */ PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1),
/* SM1ALERT# */ PAD_CFG_GPO(GPP_B23, 0, DEEP),
/* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
/* SMB_DATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
/* SMBALERT# */ PAD_CFG_GPO(GPP_C2, 0, DEEP),
/* M2_WWAN_PWREN */ PAD_CFG_GPO(GPP_C3, 0, DEEP),
/* SML0DATA */ PAD_CFG_GPI(GPP_C4, NONE, DEEP),
/* SML0ALERT# */ PAD_CFG_GPO(GPP_C5, 0, DEEP),
/* EC_IN_RW */ PAD_CFG_GPI(GPP_C6, NONE, DEEP),
/* USB_CTL */ PAD_CFG_GPO(GPP_C7, 1, DEEP),
/* UART0_RXD */ /* GPP_C8 */
/* UART0_TXD */ /* GPP_C9 */
/* NFC_RST* */ PAD_CFG_GPO(GPP_C10, 0, DEEP),
/* EN_PP3300_KEPLER */ PAD_CFG_TERM_GPO(GPP_C11, 1, 20K_PD, DEEP),
/* PCH_MEM_CFG0 */ PAD_CFG_GPI(GPP_C12, NONE, DEEP),
/* PCH_MEM_CFG1 */ PAD_CFG_GPI(GPP_C13, NONE, DEEP),
/* PCH_MEM_CFG2 */ PAD_CFG_GPI(GPP_C14, NONE, DEEP),
/* PCH_MEM_CFG3 */ PAD_CFG_GPI(GPP_C15, NONE, DEEP),
/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, 5K_PU, DEEP, NF1),
/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, 5K_PU, DEEP, NF1),
/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
/* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
/* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
/* TCH_PNL_PWREN */ PAD_CFG_GPO(GPP_C22, 1, DEEP),
/* SPI_WP_STATUS */ PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP),
/* ITCH_SPI_CS */ /* GPP_D0 */
/* ITCH_SPI_CLK */ /* GPP_D1 */
/* ITCH_SPI_MISO_1 */ /* GPP_D2 */
/* ITCH_SPI_MISO_0 */ /* GPP_D3 */
/* CAM_FLASH_STROBE */ PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1),
/* EN_PP3300_DX_EMMC */ PAD_CFG_GPO(GPP_D5, 1, DEEP),
/* EN_PP1800_DX_EMMC */ PAD_CFG_GPO(GPP_D6, 1, DEEP),
/* SH_I2C1_SDA */ PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
/* SH_I2C1_SCL */ PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
PAD_CFG_GPO(GPP_D9, 0, DEEP),
/* USB_A0_ILIM_SEL */ PAD_CFG_GPO(GPP_D10, 1, DEEP),
/* USB_A1_ILIM_SEL */ PAD_CFG_GPO(GPP_D11, 1, DEEP),
/* EN_PP3300_DX_CAM */ PAD_CFG_GPO(GPP_D12, 1, DEEP),
/* EN_PP1800_DX_AUDIO */PAD_CFG_GPO(GPP_D13, 1, DEEP),
/* ISH_UART0_TXD */ /* GPP_D14 */
/* ISH_UART0_RTS */ /* GPP_D15 */
/* ISH_UART0_CTS */ /* GPP_D16 */
/* DMIC_CLK_1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
/* DMIC_DATA_1 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
/* DMIC_CLK_0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
/* DMIC_DATA_0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
/* ITCH_SPI_D2 */ /* GPP_D21 */
/* ITCH_SPI_D3 */ /* GPP_D22 */
/* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC(GPP_E0, NONE, DEEP),
/* SATAXPCIE1 */ /* GPP_E1 */
/* SSD_PEDET */ PAD_CFG_GPI(GPP_E2, NONE, DEEP),
/* CPU_GP0 */ /* GPP_E3 */
/* SSD_SATA_DEVSLP */ PAD_CFG_GPO(GPP_E4, 0, DEEP),
/* SATA_DEVSLP1 */ /* GPP_E5 */
/* SATA_DEVSLP2 */ /* GPP_E6 */
/* TCH_PNL_INTR* */ PAD_CFG_GPI_APIC(GPP_E7, NONE, DEEP),
/* SATALED# */ /* GPP_E8 */
/* USB2_OC_0 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
/* USB2_OC_1 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
/* USB2_OC_2 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
/* USB2_OC_3 */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),
/* DDI1_HPD */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
/* DDI2_HPD */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
/* EC_SMI */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES),
/* EC_SCI */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES),
/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1),
/* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
/* DDPD_CTRLCLK */ PAD_CFG_GPI(GPP_E22, NONE, DEEP),
/* TCH_PNL_RST */ PAD_CFG_GPO(GPP_E23, 1, DEEP),
/* I2S2_SCLK */ PAD_CFG_GPI(GPP_F0, NONE, DEEP),
/* I2S2_SFRM */ PAD_CFG_GPI(GPP_F1, NONE, DEEP),
/* I2S2_TXD */ PAD_CFG_GPI(GPP_F2, NONE, DEEP),
/* I2S2_RXD */ PAD_CFG_GPI(GPP_F3, NONE, DEEP),
/* I2C2_SDA */ /* GPP_F4 */
/* I2C2_SCL */ /* GPP_F5 */
/* I2C3_SDA */ /* GPP_F6 */
/* I2C3_SCL */ /* GPP_F7 */
/* I2C4_SDA */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1),
/* I2C4_SDA */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1),
/* AUDIO_IRQ */ PAD_CFG_GPI_APIC(GPP_F10, NONE, DEEP),
/* I2C5_SCL */ /* GPP_F11 */
/* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
/* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
/* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
/* EMMC_DATA2 */ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
/* EMMC_DATA3 */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
/* EMMC_DATA4 */ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),
/* EMMC_DATA5 */ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),
/* EMMC_DATA6 */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
/* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
/* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
/* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
/* GPP_F23 */
/* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1),
/* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1),
/* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1),
/* SD_DATA2 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1),
/* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1),
/* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1),
/* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1),
/* SD_WP */ PAD_CFG_NF(GPP_G7, NONE, DEEP, NF1),
/* PCH_BATLOW */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
/* EC_PCH_ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
/* EC_PCH_WAKE */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1),
/* EC_PCH_PWRBTN */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1),
/* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
/* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
/* PM_SLP_SA# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
/* GPD7 */
/* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
/* PCH_SLP_WLAN# */ /* GPD9 */
/* PM_SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
/* LANPHYC */ /* GPD11 */
};
/* Early pad configuration in romstage. */
static const struct pad_config early_gpio_table[] = {
/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */
/* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 1, DEEP), /* EN_PP3300_KEPLER */
};
#endif
#endif
|
