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##
## This file is part of the coreboot project.
##
## Copyright (C) 2013 Google Inc.
## Copyright (C) 2015-2016 Intel Corp.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
chip soc/intel/quark
############################################################
# Set the parameters for MemoryInit
############################################################
register "AddrMode" = "0"
register "ChanMask" = "1" # Channel 0 enabled
register "ChanWidth" = "1" # 16-bit channel
register "DramDensity" = "1" # 1 Gib;
register "DramRonVal" = "0" # 34 Ohm
register "DramRttNomVal" = "2" # 120 Ohm
register "DramRttWrVal" = "0" # off
register "DramSpeed" = "0" # 800 MHz
register "DramType" = "0" # DDR3
register "DramWidth" = "0" # 8-bit
register "EccScrubBlkSize" = "2" # 64 byte blocks
register "EccScrubInterval" = "0" # ECC scrub disabled
register "Flags" = "MRC_FLAG_SCRAMBLE_EN"
register "FspReservedMemoryLength" = "0x00100000" # Size in bytes
register "RankMask" = "1" # RANK 0 enabled
register "SmmTsegSize" = "0" # SMM Region size in MiB
register "SocRdOdtVal" = "0" # off
register "SocWrRonVal" = "1" # 32 Ohm
register "SocWrSlewRate" = "1" # 4V/nSec
register "SrInt" = "3" # 7.8 uSec
register "SrTemp" = "0" # normal
register "tCL" = "6" # clocks
register "tFAW" = "40000" # picoseconds
register "tRAS" = "37500" # picoseconds
register "tRRD" = "10000" # picoseconds
register "tWTR" = "10000" # picoseconds
############################################################
# Enable the devices
############################################################
device domain 0 on
# EDS Table 3
device pci 00.0 on end # 8086 0958 - Host Bridge
device pci 14.0 on end # 8086 08A7 - SD/SDIO/eMMC controller
device pci 14.1 off end # 8086 0936 - HSUART 0
device pci 14.2 on end # 8086 0939 - USB 2.0 Device port
device pci 14.3 on end # 8086 0939 - USB EHCI Host controller
device pci 14.4 on end # 8086 093A - USB OHCI Host controller
device pci 14.5 on end # 8086 0936 - HSUART 1
device pci 14.6 off end # 8086 0937 - 10/100 Ethernet MAC 0
device pci 14.7 off end # 8086 0937 - 10/100 Ethernet MAC 1
device pci 15.0 on end # 8086 0935 - SPI controller 0
device pci 15.1 on end # 8086 0935 - SPI controller 1
device pci 15.2 on end # 8086 0934 - I2C/GPIO controller
device pci 17.0 on end # 8086 11C3 - PCIe Root Port 0
device pci 17.1 off end # 8086 11C4 - PCIe Root Port 1
device pci 1f.0 on end # 8086 095E - Legacy Bridge
end
end
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