blob: 4f9e86d7a9ae27f65829a04984363cdadb6ef8c4 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
|
##
## This file is part of the coreboot project.
##
##
## SPDX-License-Identifier: GPL-2.0-only
if BOARD_INTEL_D945GCLF
config BOARD_SPECIFIC_OPTIONS
def_bool y
select CPU_INTEL_SOCKET_441
select NORTHBRIDGE_INTEL_I945
select NORTHBRIDGE_INTEL_SUBTYPE_I945GC
select SOUTHBRIDGE_INTEL_I82801GX
select SUPERIO_SMSC_LPC47M15X
select HAVE_OPTION_TABLE
select HAVE_CMOS_DEFAULT
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select HAVE_ACPI_TABLES
select HAVE_ACPI_RESUME
select BOARD_ROMSIZE_KB_512
select MAINBOARD_HAS_NATIVE_VGA_INIT
select INTEL_GMA_HAVE_VBT
config MAINBOARD_DIR
string
default "intel/d945gclf"
config MAINBOARD_PART_NUMBER
string
default "D945GCLF"
config IRQ_SLOT_COUNT
int
default 18
config MAX_CPUS
int
default 4
endif # BOARD_INTEL_D945GCLF
|