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config BOARD_INTEL_ADLRVP_COMMON
def_bool n
select ALDERLAKE_A0_CONFIGURE_PMC_DESCRIPTOR
select BOARD_ROMSIZE_KB_32768
select DRIVERS_I2C_GENERIC
select DRIVERS_I2C_HID
select DRIVERS_I2C_MAX98373
select DRIVERS_INTEL_DPTF
select DRIVERS_INTEL_MIPI_CAMERA
select DRIVERS_INTEL_SOUNDWIRE
select DRIVERS_SOUNDWIRE_ALC711
select DRIVERS_SPI_ACPI
select DRIVERS_USB_ACPI
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select HAVE_SPD_IN_CBFS
select MAINBOARD_HAS_CHROMEOS
select SOC_INTEL_COMMON_BLOCK_IPU
select SOC_INTEL_CSE_LITE_SKU
select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
config BOARD_INTEL_ADLRVP_P
select BOARD_INTEL_ADLRVP_COMMON
select DRIVERS_UART_8250IO
select MAINBOARD_USES_IFD_EC_REGION
select SOC_INTEL_ALDERLAKE_PCH_P
select GEN3_EXTERNAL_CLOCK_BUFFER
config BOARD_INTEL_ADLRVP_P_EXT_EC
select BOARD_INTEL_ADLRVP_COMMON
select DRIVERS_INTEL_PMC
select INTEL_LPSS_UART_FOR_CONSOLE
select SOC_INTEL_ALDERLAKE_PCH_P
select GEN3_EXTERNAL_CLOCK_BUFFER
config BOARD_INTEL_ADLRVP_P_MCHP
select BOARD_INTEL_ADLRVP_COMMON
select DRIVERS_INTEL_MIPI_CAMERA
select DRIVERS_INTEL_PMC
select EC_GOOGLE_CHROMEEC_ACPI_MEMMAP
select EC_GOOGLE_CHROMEEC_MEC
select INTEL_LPSS_UART_FOR_CONSOLE
select SOC_INTEL_ALDERLAKE_PCH_P
config BOARD_INTEL_ADLRVP_M
select BOARD_INTEL_ADLRVP_COMMON
select DRIVERS_UART_8250IO
select MAINBOARD_USES_IFD_EC_REGION
select SOC_INTEL_ALDERLAKE_PCH_M
config BOARD_INTEL_ADLRVP_M_EXT_EC
select BOARD_INTEL_ADLRVP_COMMON
select DRIVERS_INTEL_PMC
select FW_CONFIG
select FW_CONFIG_SOURCE_CHROMEEC_CBI
select INTEL_LPSS_UART_FOR_CONSOLE
select MAINBOARD_HAS_SPI_TPM_CR50
select MAINBOARD_HAS_TPM2
select SOC_INTEL_ALDERLAKE_PCH_M
select SPI_TPM
config BOARD_INTEL_ADLRVP_N
select BOARD_INTEL_ADLRVP_COMMON
select DRIVERS_UART_8250IO
select MAINBOARD_USES_IFD_EC_REGION
select SOC_INTEL_ALDERLAKE_PCH_N
config BOARD_INTEL_ADLRVP_N_EXT_EC
select BOARD_INTEL_ADLRVP_COMMON
select DRIVERS_INTEL_PMC
select INTEL_LPSS_UART_FOR_CONSOLE
select SOC_INTEL_ALDERLAKE_PCH_N
if BOARD_INTEL_ADLRVP_COMMON
config CHROMEOS
select GBB_FLAG_FORCE_DEV_SWITCH_ON
select GBB_FLAG_FORCE_DEV_BOOT_USB
select GBB_FLAG_FORCE_DEV_BOOT_ALTFW
select GBB_FLAG_FORCE_MANUAL_RECOVERY
select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC
select HAS_RECOVERY_MRC_CACHE
config MAINBOARD_DIR
default "intel/adlrvp"
config VARIANT_DIR
default "adlrvp_p" if BOARD_INTEL_ADLRVP_P
default "adlrvp_p_ext_ec" if BOARD_INTEL_ADLRVP_P_EXT_EC
default "adlrvp_p_mchp" if BOARD_INTEL_ADLRVP_P_MCHP
default "adlrvp_m" if BOARD_INTEL_ADLRVP_M
default "adlrvp_m_ext_ec" if BOARD_INTEL_ADLRVP_M_EXT_EC
default "adlrvp_n" if BOARD_INTEL_ADLRVP_N
default "adlrvp_n_ext_ec" if BOARD_INTEL_ADLRVP_N_EXT_EC
config GBB_HWID
string
depends on CHROMEOS
default "ADLRVPM" if BOARD_INTEL_ADLRVP_M || BOARD_INTEL_ADLRVP_M_EXT_EC
default "ADLRVPN" if BOARD_INTEL_ADLRVP_N || BOARD_INTEL_ADLRVP_N_EXT_EC
default "ADLRVPP"
config MAINBOARD_PART_NUMBER
default "Alder Lake Client Platform"
config MAINBOARD_VENDOR
string
default "Intel Corporation"
config MAINBOARD_FAMILY
string
default "Intel_adlrvp"
config DEVICETREE
default "devicetree_m.cb" if BOARD_INTEL_ADLRVP_M || BOARD_INTEL_ADLRVP_M_EXT_EC
default "devicetree_n.cb" if BOARD_INTEL_ADLRVP_N || BOARD_INTEL_ADLRVP_N_EXT_EC
default "devicetree.cb"
config OVERRIDE_DEVICETREE
default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
config DIMM_SPD_SIZE
default 512
choice
prompt "ON BOARD EC"
default ADL_INTEL_EC if BOARD_INTEL_ADLRVP_P || BOARD_INTEL_ADLRVP_M || BOARD_INTEL_ADLRVP_N
default ADL_CHROME_EC if BOARD_INTEL_ADLRVP_P_EXT_EC || BOARD_INTEL_ADLRVP_M_EXT_EC || BOARD_INTEL_ADLRVP_P_MCHP || BOARD_INTEL_ADLRVP_N_EXT_EC
help
This option allows you to select the on board EC to use.
Select whether the board has Intel EC or Chrome EC
config ADL_CHROME_EC
bool "Chrome EC"
select EC_GOOGLE_CHROMEEC
select EC_GOOGLE_CHROMEEC_ESPI
select EC_GOOGLE_CHROMEEC_BOARDID
select EC_ACPI
select EC_GOOGLE_CHROMEEC_LPC
config ADL_INTEL_EC
bool "Intel EC"
select EC_ACPI
endchoice
config VBOOT
select VBOOT_LID_SWITCH
select VBOOT_MOCK_SECDATA if BOARD_INTEL_ADLRVP_P_EXT_EC
select EC_GOOGLE_CHROMEEC_SWITCHES if ADL_CHROME_EC
select VBOOT_EARLY_EC_SYNC if BOARD_INTEL_ADLRVP_M_EXT_EC
config UART_FOR_CONSOLE
int
default 0
config DRIVER_TPM_SPI_BUS
default 0x2 if BOARD_INTEL_ADLRVP_M_EXT_EC
config TPM_TIS_ACPI_INTERRUPT
int
default 67 if BOARD_INTEL_ADLRVP_M_EXT_EC # GPE0_DW2_3 (GPP_E3)
config GEN3_EXTERNAL_CLOCK_BUFFER
bool
depends on SOC_INTEL_ALDERLAKE_PCH_P
default n
help
Support external Gen-3 clock chip for ADL-P.
`CONFIG_CLKSRC_FOR_EXTERNAL_BUFFER` provides feed clock to discrete buffer
for further distribution to platform. SRCCLKREQB[7:9] maps to internal
SRCCLKREQB[6]. If any of them asserted, SRC buffer
`CONFIG_CLKSRC_FOR_EXTERNAL_BUFFER` gets enabled.
config CLKSRC_FOR_EXTERNAL_BUFFER
depends on GEN3_EXTERNAL_CLOCK_BUFFER
int
default 6 # CLKSRC 6
endif
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