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##
## This file is part of the coreboot project.
##
## Copyright (C) 2012 Ricardo Martins <rasmartins@gmail.com>
##
## This program is free software; you can redistribute it and/or
## modify it under the terms of the GNU General Public License as
## published by the Free Software Foundation; version 2 of
## the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc.
##
chip northbridge/amd/lx
device domain 0 on
device pci 1.0 on end # Northbridge
device pci 1.1 on end # Video Adapter
device pci 1.2 on end # AES Security Block
chip southbridge/amd/cs5536
register "lpc_serirq_enable" = "0x000010da"
register "lpc_serirq_polarity" = "0x0000ef25"
register "lpc_serirq_mode" = "1"
register "enable_gpio_int_route" = "0x0d0c0700"
register "enable_ide_nand_flash" = "0"
register "enable_USBP4_device" = "0" # 0:host, 1:device
register "enable_USBP4_overcurrent" = "0"
register "com1_enable" = "0"
register "com2_enable" = "0"
register "unwanted_vpci[0]" = "0" # End of list has a zero
device pci 11.0 on end # IT8888
device pci e.0 on end # RTL8100C
device pci f.0 on # ISA Bridge
chip superio/smsc/smscsuperio # SMSC SCH3114
device pnp 2e.0 on # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
device pnp 2e.3 on # Parallel port
io 0x60 = 0x378
irq 0x70 = 7
end
device pnp 2e.4 on # COM1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.5 on # COM2
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.7 on # PS/2 keyboard/mouse
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1 # Keyboard
irq 0x72 = 12 # Mouse
end
device pnp 2e.a on # Runtime Register
io 0x60 = 0x400
end
end
end
device pci f.2 on end # IDE Controller
device pci f.3 on end # Audio
device pci f.4 on end # OHCI
device pci f.5 on end # EHCI
end
end
# APIC cluster is late CPU init.
device cpu_cluster 0 on
chip cpu/amd/geode_lx
device lapic 0 on end
end
end
end
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