blob: 36db67bf49bcf647503d5ba2b186da226dce0bb0 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
|
##
## This file is part of the coreboot project.
##
## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
if BOARD_IEI_NOVA_4899R
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
select CPU_AMD_GEODE_GX1
select NORTHBRIDGE_AMD_GX1
select SOUTHBRIDGE_AMD_CS5530
select SUPERIO_WINBOND_W83977TF
select ROMCC
select HAVE_PIRQ_TABLE
select PIRQ_ROUTE
select HAVE_OPTION_TABLE
select UDELAY_TSC
select BOARD_ROMSIZE_KB_256
config MAINBOARD_DIR
string
default iei/nova4899r
config MAINBOARD_PART_NUMBER
string
default "NOVA-4899R"
config IRQ_SLOT_COUNT
int
default 5
endif # BOARD_IEI_NOVA_4899R
|
