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FLASH 32M {
SI_ALL 5M {
SI_DESC 4K
SI_ME
}
SI_BIOS 27M {
RW_SECTION_A 8M {
VBLOCK_A 64K
FW_MAIN_A(CBFS)
RW_FWID_A 64
ME_RW_A(CBFS) 3M
}
RW_LEGACY(CBFS) 2M
RW_MISC 1M {
UNIFIED_MRC_CACHE(PRESERVE) 192K {
RECOVERY_MRC_CACHE 64K
RW_MRC_CACHE 128K
}
RW_ELOG(PRESERVE) 4K
RW_SHARED 16K {
SHARED_DATA 8K
VBLOCK_DEV 8K
}
RW_VPD(PRESERVE) 8K
RW_NVRAM(PRESERVE) 24K
}
# Starts at 16M boundary in the SPI flash.
# No region can be placed across the 16M boundary
# because the SPI flash is mapped into separate
# non-contiguous mmap windows
RW_SECTION_B 8M {
VBLOCK_B 64K
FW_MAIN_B(CBFS)
RW_FWID_B 64
ME_RW_B(CBFS) 3M
}
# Make WP_RO region align with SPI vendor
# memory protected range specification.
WP_RO 8M {
RO_VPD(PRESERVE) 16K
RO_SECTION {
FMAP 2K
RO_FRID 64
GBB@4K 448K
COREBOOT(CBFS)
}
}
}
}
|
