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##
## This file is part of the coreboot project.
##
##
## SPDX-License-Identifier: GPL-2.0-only
chip soc/nvidia/tegra210
device cpu_cluster 0 on
end
register "display_controller" = "TEGRA_ARM_DISPLAYA"
register "xres" = "2560"
register "yres" = "1800"
# bits per pixel and color depth
register "framebuffer_bits_per_pixel" = "32"
register "color_depth" = "12"
# framebuffer resolution
register "display_xres" = "1280"
register "display_yres" = "800"
register "href_to_sync" = "1"
register "hfront_porch" = "80"
register "hsync_width" = "80"
register "hback_porch" = "80"
register "vref_to_sync" = "1"
register "vfront_porch" = "4"
register "vsync_width" = "4"
register "vback_porch" = "4"
register "refresh" = "60"
# use value from kernel driver
register "pixel_clock" = "304416000"
register "win_opt" = "DSI_ENABLE"
end
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