blob: 47edc62397b4a44b9e032b7f7b99d94e3a987f63 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
|
chip northbridge/intel/haswell
# Set panel power delays
register "gpu_panel_power_cycle_delay_ms" = "400"
register "gpu_panel_power_up_delay_ms" = "40"
register "gpu_panel_power_down_delay_ms" = "15"
register "gpu_panel_power_backlight_on_delay_ms" = "210"
register "gpu_panel_power_backlight_off_delay_ms" = "210"
device domain 0 on
chip southbridge/intel/lynxpoint
# DTLE DATA / EDGE values
register "sata_port0_gen3_dtle" = "0x5"
register "sata_port1_gen3_dtle" = "0x5"
# Disable PCIe CLKOUT 2-5 and CLKOUT_XDP
register "icc_clock_disable" = "0x013c0000"
end
end
end
|
