1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
|
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <amdblocks/acpimmio.h>
#include <amdblocks/amd_pci_util.h>
#include <amdblocks/psp.h>
#include <amdblocks/xhci.h>
#include <baseboard/variants.h>
#include <console/console.h>
#include <cpu/x86/smm.h>
#include <device/device.h>
#include <drivers/i2c/tpm/chip.h>
#include <soc/acpi.h>
#include <variant/ec.h>
/* The IRQ mapping in fch_irq_map ends up getting written to the indirect address space that is
accessed via I/O ports 0xc00/0xc01. */
/*
* This controls the device -> IRQ routing.
*
* Hardcoded IRQs:
* 0: timer < soc/amd/common/acpi/lpc.asl
* 1: i8042 - Keyboard
* 2: cascade
* 8: rtc0 <- soc/amd/common/acpi/lpc.asl
* 9: acpi <- soc/amd/common/acpi/lpc.asl
*/
static const struct fch_irq_routing fch_irq_map[] = {
{ PIRQ_A, 12, PIRQ_NC },
{ PIRQ_B, 14, PIRQ_NC },
{ PIRQ_C, 15, PIRQ_NC },
{ PIRQ_D, 12, PIRQ_NC },
{ PIRQ_E, 14, PIRQ_NC },
{ PIRQ_F, 15, PIRQ_NC },
{ PIRQ_G, 12, PIRQ_NC },
{ PIRQ_H, 14, PIRQ_NC },
{ PIRQ_SCI, ACPI_SCI_IRQ, ACPI_SCI_IRQ },
{ PIRQ_SD, PIRQ_NC, PIRQ_NC },
{ PIRQ_SDIO, PIRQ_NC, PIRQ_NC },
{ PIRQ_GPIO, 11, 11 },
{ PIRQ_I2C0, 10, 10 },
{ PIRQ_I2C1, 7, 7 },
{ PIRQ_I2C2, 6, 6 },
{ PIRQ_I2C3, 5, 5 },
{ PIRQ_UART0, 4, 4 },
{ PIRQ_UART1, 3, 3 },
/* The MISC registers are not interrupt numbers */
{ PIRQ_MISC, 0xfa, 0x00 },
{ PIRQ_MISC0, 0x91, 0x00 },
{ PIRQ_HPET_L, 0x00, 0x00 },
{ PIRQ_HPET_H, 0x00, 0x00 },
};
const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length)
{
*length = ARRAY_SIZE(fch_irq_map);
return fch_irq_map;
}
static void mainboard_configure_gpios(void)
{
size_t base_num_gpios, override_num_gpios;
const struct soc_amd_gpio *base_gpios, *override_gpios;
baseboard_gpio_table(&base_gpios, &base_num_gpios);
variant_override_gpio_table(&override_gpios, &override_num_gpios);
gpio_configure_pads_with_override(base_gpios, base_num_gpios,
override_gpios, override_num_gpios);
}
static void configure_psp_tpm_gpio(void)
{
const struct device *ti50_dev = DEV_PTR(ti50);
struct drivers_i2c_tpm_config *cfg = config_of(ti50_dev);
psp_set_tpm_irq_gpio(cfg->irq_gpio.pins[0]);
}
static void mainboard_init(void *chip_info)
{
mainboard_configure_gpios();
mainboard_ec_init();
configure_psp_tpm_gpio();
}
static void mainboard_enable(struct device *dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
/* TODO: b/184678786 - Move into espi_config */
/* Unmask eSPI IRQ 1 (Keyboard) */
pm_write32(PM_ESPI_INTR_CTRL, PM_ESPI_DEV_INTR_MASK & ~(BIT(1)));
}
void smm_mainboard_pci_resource_store_init(struct smm_pci_resource_info *slots, size_t size)
{
soc_xhci_store_resources(slots, size);
}
struct chip_operations mainboard_ops = {
.init = mainboard_init,
.enable_dev = mainboard_enable,
};
|
