blob: 37785fd92d7d3c3c629e7f7cb0be6aba1acc2e4f (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
|
FLASH 32M {
SI_ALL 8M {
SI_DESC 16K
SI_ME
}
SI_BIOS 24M {
RW_SECTION_A 7680K {
VBLOCK_A 8K
FW_MAIN_A(CBFS)
RW_FWID_A 64
ME_RW_A(CBFS) 4000K
}
RW_MISC 1M {
UNIFIED_MRC_CACHE(PRESERVE) 128K {
RECOVERY_MRC_CACHE 64K
RW_MRC_CACHE 64K
}
RW_ELOG(PRESERVE) 16K
RW_SHARED 16K {
SHARED_DATA 8K
VBLOCK_DEV 8K
}
# The RW_SPD_CACHE region is only used for rex variants that use DDRx memory.
# It is placed in the common `chromeos.fmd` file because it is only 4K and there
# is free space in the RW_MISC region that cannot be easily reclaimed because
# the RW_SECTION_B must start on the 16M boundary.
RW_SPD_CACHE(PRESERVE) 4K
RW_VPD(PRESERVE) 8K
RW_NVRAM(PRESERVE) 24K
}
# This section starts at the 16M boundary in SPI flash.
# MTL does not support a region crossing this boundary,
# because the SPI flash is memory-mapped into two non-
# contiguous windows.
RW_SECTION_B 7680K {
VBLOCK_B 8K
FW_MAIN_B(CBFS)
RW_FWID_B 64
ME_RW_B(CBFS) 4000K
}
RW_LEGACY(CBFS) 1M
RW_UNUSED 3M
# Make WP_RO region align with SPI vendor
# memory protected range specification.
WP_RO 4M {
RO_VPD(PRESERVE) 16K
RO_GSCVD 8K
RO_SECTION {
FMAP 2K
RO_FRID 64
GBB@4K 12K
COREBOOT(CBFS)
}
}
}
}
|
