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/*
* This file is part of the coreboot project.
*
* Copyright 2016 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <soc/meminit.h>
#include <soc/romstage.h>
static const struct lpddr4_swizzle_cfg board_swizzle = {
/* CH0_DQA[0:31] SoC pins -> U22 LPDDR4 module pins */
.phys[LP4_PHYS_CH0A] = {
/* DQA[0:7] pins of LPDDR4 module. */
.dqs[LP4_DQS0] = { 6, 7, 5, 4, 3, 1, 0, 2 },
/* DQA[8:15] pins of LPDDR4 module. */
.dqs[LP4_DQS1] = { 12, 10, 11, 13, 14, 8, 9, 15 },
/* DQB[0:7] pins of LPDDR4 module with offset of 16. */
.dqs[LP4_DQS2] = { 16, 22, 23, 20, 18, 17, 19, 21 },
/* DQB[7:15] pins of LPDDR4 module with offset of 16. */
.dqs[LP4_DQS3] = { 30, 28, 29, 25, 24, 26, 27, 31 },
},
.phys[LP4_PHYS_CH0B] = {
/* DQA[0:7] pins of LPDDR4 module. */
.dqs[LP4_DQS0] = { 7, 3, 5, 2, 6, 0, 1, 4 },
/* DQA[8:15] pins of LPDDR4 module. */
.dqs[LP4_DQS1] = { 9, 14, 12, 13, 10, 11, 8, 15 },
/* DQB[0:7] pins of LPDDR4 module with offset of 16. */
.dqs[LP4_DQS2] = { 20, 22, 23, 16, 19, 17, 18, 21 },
/* DQB[7:15] pins of LPDDR4 module with offset of 16. */
.dqs[LP4_DQS3] = { 28, 24, 26, 27, 29, 30, 31, 25 },
},
.phys[LP4_PHYS_CH1A] = {
/* DQA[0:7] pins of LPDDR4 module. */
.dqs[LP4_DQS0] = { 2, 1, 6, 7, 5, 4, 3, 0 },
/* DQA[8:15] pins of LPDDR4 module. */
.dqs[LP4_DQS1] = { 11, 10, 8, 9, 12, 15, 13, 14 },
/* DQB[0:7] pins of LPDDR4 module with offset of 16. */
.dqs[LP4_DQS2] = { 17, 23, 19, 16, 21, 22, 20, 18 },
/* DQB[7:15] pins of LPDDR4 module with offset of 16. */
.dqs[LP4_DQS3] = { 31, 29, 26, 25, 28, 27, 24, 30 },
},
.phys[LP4_PHYS_CH1B] = {
/* DQA[0:7] pins of LPDDR4 module. */
.dqs[LP4_DQS0] = { 4, 3, 7, 5, 6, 1, 0, 2 },
/* DQA[8:15] pins of LPDDR4 module. */
.dqs[LP4_DQS1] = { 15, 9, 8, 11, 14, 13, 12, 10 },
/* DQB[0:7] pins of LPDDR4 module with offset of 16. */
.dqs[LP4_DQS2] = { 20, 23, 22, 21, 18, 19, 16, 17 },
/* DQB[7:15] pins of LPDDR4 module with offset of 16. */
.dqs[LP4_DQS3] = { 25, 28, 30, 31, 26, 27, 24, 29 },
},
};
void mainboard_memory_init_params(struct FSPM_UPD *memupd)
{
struct FSP_M_CONFIG *cfg = &memupd->FspmConfig;
/* Use a default 2400 speed. */
meminit_lpddr4(cfg, LP4_SPEED_2400);
/* Enable both logical channels with a 8Gb density. */
meminit_lpddr4_enable_channel(cfg, LP4_LCH0, LP4_8Gb_DENSITY,
&board_swizzle);
meminit_lpddr4_enable_channel(cfg, LP4_LCH1, LP4_8Gb_DENSITY,
&board_swizzle);
}
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