blob: 1471e2a8991dfffd132f5d6f3a8fdc4254dcf2c0 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
|
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */
#define ENABLE_TPM
#include <acpi/acpi.h>
DefinitionBlock(
"dsdt.aml",
"DSDT",
0x02, // DSDT revision: ACPI v2.0 and up
OEM_ID,
ACPI_TABLE_CREATOR,
0x20110725 // OEM revision
)
{
#include <soc/intel/baytrail/acpi/platform.asl>
// global NVS and variables
#include <soc/intel/baytrail/acpi/globalnvs.asl>
#include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) {
Device (PCI0)
{
//#include <soc/intel/baytrail/acpi/northcluster.asl>
#include <soc/intel/baytrail/acpi/southcluster.asl>
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
}
/* Dynamic Platform Thermal Framework */
#include "acpi/dptf.asl"
}
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
#include <southbridge/intel/common/acpi/sleepstates.asl>
#include "acpi/mainboard.asl"
}
|
