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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2015-2017 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <variant/ec.h>
/* DefinitionBlock Statement */
DefinitionBlock (
"DSDT.AML", /* Output filename */
"DSDT", /* Signature */
0x02, /* DSDT Revision, needs to be 2 for 64bit */
"GOOGLE ", /* OEMID */
"COREBOOT", /* TABLE ID */
0x00010001 /* OEM Revision */
)
{ /* Start of ASL file */
/* #include <arch/x86/acpi/debug.asl> */ /* as needed */
/* global NVS and variables */
#include <globalnvs.asl>
/* Globals for the platform */
#include <variant/acpi/mainboard.asl>
/* PCI IRQ mapping for the Southbridge */
#include <pcie.asl>
/* Describe the processor tree (\_PR) */
#include <cpu.asl>
/* Contains the supported sleep states for this chipset */
#include <sleepstates.asl>
/* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
#include <variant/acpi/sleep.asl>
/* System Bus */
Scope(\_SB) { /* Start \_SB scope */
/* global utility methods expected within the \_SB scope */
#include <arch/x86/acpi/globutil.asl>
/* IRQ Routing mapping for this platform (in \_SB scope) */
#include <variant/acpi/routing.asl>
Device(PWRB) {
Name(_HID, EISAID("PNP0C0C"))
Name(_UID, 0xAA)
}
/* Describe the SOC */
#include <soc.asl>
} /* End \_SB scope */
/* Thermal handler */
#include <variant/acpi/thermal.asl>
/* Chrome OS specific */
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
/* Chrome OS Embedded Controller */
Scope (\_SB.PCI0.LPCB)
{
/* ACPI code for EC SuperIO functions */
#include <ec/google/chromeec/acpi/superio.asl>
/* ACPI code for EC functions */
#include <ec/google/chromeec/acpi/ec.asl>
}
/* Describe SMBUS for the Southbridge */
#include <smbus.asl>
/* Define the General Purpose Events for the platform */
#include <variant/acpi/gpe.asl>
}
/* End of ASL file */
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