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/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */
#include <arch/acpi.h>
#include <console/console.h>
#include <cpu/x86/smm.h>
#include <soc/pm.h>
#include <ec/google/chromeec/ec.h>
#include <soc/gpio.h>
#include <soc/iomap.h>
#include <soc/nvs.h>
#include "onboard.h"
int mainboard_io_trap_handler(int smif)
{
switch (smif) {
case 0x99:
printk(BIOS_DEBUG, "Sample\n");
smm_get_gnvs()->smif = 0;
break;
default:
return 0;
}
/* On success, the IO Trap Handler returns 0
* On failure, the IO Trap Handler returns a value != 0
*
* For now, we force the return value to 0 and log all traps to
* see what's going on.
*/
return 1;
}
/* gpi_sts is GPIO 47:32 */
void mainboard_smi_gpi(u32 gpi_sts)
{
}
void mainboard_smi_sleep(u8 slp_typ)
{
/* Disable USB charging if required */
switch (slp_typ) {
case ACPI_S3:
set_power_led(LED_BLINK);
/* Enable DCP mode */
if (CONFIG(BOARD_GOOGLE_TIDUS)) {
set_gpio(GPIO_USB_CTL_1, 0);
}
break;
case ACPI_S5:
set_power_led(LED_OFF);
break;
}
}
int mainboard_smi_apmc(u8 apmc)
{
switch (apmc) {
case APM_CNT_ACPI_ENABLE:
break;
case APM_CNT_ACPI_DISABLE:
break;
}
return 0;
}
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