1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
|
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <mainboard/google/jecht/onboard.h>
/*
* LAN connected to Root Port 3, becomes Root Port 1 after coalesce
*/
Scope (\_SB.PCI0.RP01)
{
Device (ETH0)
{
Name (_ADR, 0x00000000)
Name (_PRW, Package() { JECHT_NIC_WAKE_GPIO, 3 })
Method (_DSW, 3, NotSerialized)
{
Store (JECHT_NIC_WAKE_GPIO, Local0)
If (LEqual (Arg0, 1)) {
// Enable GPIO as wake source
\_SB.PCI0.LPCB.GPIO.GWAK (Local0)
}
}
}
}
/*
* WLAN connected to Root Port 4, becomes Root Port 2 after coalesce
*/
Scope (\_SB.PCI0.RP02)
{
Device (WLAN)
{
Name (_ADR, 0x00000000)
Name (_PRW, Package() { JECHT_WLAN_WAKE_GPIO, 3 })
Method (_DSW, 3, NotSerialized)
{
Store (JECHT_WLAN_WAKE_GPIO, Local0)
If (LEqual (Arg0, 1)) {
// Enable GPIO as wake source
\_SB.PCI0.LPCB.GPIO.GWAK (Local0)
}
}
}
}
/* USB port entries */
#include <variant/acpi/usb.asl>
|
