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chip soc/intel/cannonlake
# GPE configuration
# Note that GPE events called out in ASL code rely on this
# route. i.e. If this route changes then the affected GPE
# offset bits also need to be changed.
# DW1 is used by:
# - GPP_C21 - H1_PCH_INT_ODL
register "gpe0_dw0" = "PMC_GPP_A"
register "gpe0_dw1" = "PMC_GPP_C"
register "gpe0_dw2" = "PMC_GPP_D"
# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
register "gen1_dec" = "0x00fc0801"
register "gen2_dec" = "0x000c0201"
# EC memory map range is 0x900-0x9ff
register "gen3_dec" = "0x00fc0901"
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| GSPI0 | cr50 TPM. Early init is |
#| | required to set up a BAR |
#| | for TPM communication |
#| | before memory is up |
#| I2C0 | Touchpad |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.gspi[0] = {
.speed_mhz = 1,
.early_init = 1,
},
.i2c[0] = {
.speed = I2C_SPEED_FAST,
},
}"
# FSP configuration
register "InternalGfx" = "1"
register "SkipExtGfxScan" = "1"
device domain 0 on
device pci 00.0 off end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device
device pci 04.0 off end # SA Thermal device
device pci 12.0 off end # Thermal Subsystem
device pci 12.5 off end # UFS SCS
device pci 12.6 off end # GSPI #2
device pci 14.0 off end # USB xHCI
device pci 14.1 off end # USB xDCI (OTG)
device pci 14.5 off end # SDCard
device pci 15.0 on
chip drivers/i2c/generic
register "hid" = ""ELAN0000""
register "desc" = ""ELAN Touchpad""
register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A21_IRQ)"
device i2c 15 on end
end
end # I2C #0
device pci 15.1 off end # I2C #1
device pci 15.2 off end # I2C #2
device pci 15.3 off end # I2C #3
device pci 16.0 off end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R
device pci 16.3 off end # Management Engine KT Redirection
device pci 16.4 off end # Management Engine Interface 3
device pci 16.5 off end # Management Engine Interface 4
device pci 17.0 off end # SATA
device pci 19.0 off end # I2C #4
device pci 19.1 off end # I2C #5
device pci 19.2 off end # UART #2
device pci 1a.0 off end # eMMC
device pci 1c.0 off end # PCI Express Port 1 (USB)
device pci 1c.1 off end # PCI Express Port 2 (USB)
device pci 1c.2 off end # PCI Express Port 3 (USB)
device pci 1c.3 off end # PCI Express Port 4 (USB)
device pci 1c.4 off end # PCI Express Port 5 (USB)
device pci 1c.5 off end # PCI Express Port 6
device pci 1c.6 off end # PCI Express Port 7
device pci 1c.7 off end # PCI Express Port 8
device pci 1d.0 off end # PCI Express Port 9
device pci 1d.1 off end # PCI Express Port 10
device pci 1d.2 off end # PCI Express Port 11
device pci 1d.3 off end # PCI Express Port 12
device pci 1d.4 off end # PCI Express Port 13 (x4)
device pci 1e.0 on end # UART #0
device pci 1e.1 off end # UART #1
device pci 1e.2 on
chip drivers/spi/acpi
register "hid" = "ACPI_DT_NAMESPACE_HID"
register "compat_string" = ""google,cr50""
register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C21_IRQ)"
device spi 0 on end
end
end # GSPI #0
device pci 1e.3 off end # GSPI #1
device pci 1f.0 on end # LPC/eSPI
device pci 1f.1 off end # P2SB
device pci 1f.2 off end # Power Management Controller
device pci 1f.3 off end # Intel HDA
device pci 1f.4 off end # SMBus
device pci 1f.5 off end # PCH SPI
device pci 1f.6 off end # GbE
end
end
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