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chip soc/intel/skylake
# Enable deep Sx states
register "deep_s3_enable" = "1"
register "deep_s5_enable" = "1"
register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
# Must leave UART0 enabled or SD/eMMC will not work as PCI
register "SerialIoDevMode" = "{ \
[PchSerialIoIndexI2C0] = PchSerialIoPci, \
[PchSerialIoIndexI2C1] = PchSerialIoPci, \
[PchSerialIoIndexI2C2] = PchSerialIoDisabled, \
[PchSerialIoIndexI2C3] = PchSerialIoDisabled, \
[PchSerialIoIndexI2C4] = PchSerialIoPci, \
[PchSerialIoIndexI2C5] = PchSerialIoDisabled, \
[PchSerialIoIndexSpi0] = PchSerialIoDisabled, \
[PchSerialIoIndexSpi1] = PchSerialIoDisabled, \
[PchSerialIoIndexUart0] = PchSerialIoPci, \
[PchSerialIoIndexUart1] = PchSerialIoDisabled, \
[PchSerialIoIndexUart2] = PchSerialIoPci, \
}"
register "PortUsb20Enable[0]" = "1" # Type-C Port 1
register "PortUsb20Enable[1]" = "1" # Type-C Port 2
register "PortUsb20Enable[2]" = "1" # Bluetooth
register "PortUsb20Enable[4]" = "1" # Type-A Port 1
register "PortUsb20Enable[6]" = "1" # Camera
register "PortUsb20Enable[8]" = "1" # Type-A Port 2
register "PortUsb30Enable[0]" = "1" # Type-C Port 1
register "PortUsb30Enable[1]" = "1" # Type-C Port 2
register "PortUsb30Enable[2]" = "1" # Type-A Port 1
register "PortUsb30Enable[3]" = "1" # Type-A Port 2
# Enable Root port 1 and 5.
register "PcieRpEnable[0]" = "1"
register "PcieRpEnable[4]" = "1"
# Enable CLKREQ#
register "PcieRpClkReqSupport[0]" = "1"
register "PcieRpClkReqSupport[4]" = "1"
# RP 1 uses SRCCLKREQ1# while RP 5 uses SRCCLKREQ2#
register "PcieRpClkReqNumber[0]" = "1"
register "PcieRpClkReqNumber[4]" = "2"
register "ScsEmmcEnabled" = "1"
register "ScsEmmcHs400Enabled" = "0"
register "ScsSdCardEnabled" = "1"
register "EnableAzalia" = "1"
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "ProbelessTrace" = "0"
register "EnableTraceHub" = "0"
register "EnableLan" = "0"
register "EnableSata" = "0"
register "IshEnable" = "0"
register "XdciEnable" = "0"
register "SsicPortEnable" = "0"
register "SmbusEnable" = "1"
register "Cio2Enable" = "0"
register "PttSwitch" = "0"
register "SkipExtGfxScan" = "1"
# GPE configuration
# Note that GPE events called out in ASL code rely on this
# route. i.e. If this route changes then the affected GPE
# offset bits also need to be changed.
register "gpe0_dw0" = "GPP_C"
register "gpe0_dw1" = "GPP_D"
register "gpe0_dw2" = "GPP_E"
# Embedded Controller host command window
register "gen1_dec" = "0x00fc0801"
device cpu_cluster 0 on
device lapic 0 on end
end
device domain 0 on
device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device
device pci 14.0 on end # USB 3.0 xHCI Controller
device pci 14.1 off end # USB Device Controller (OTG)
device pci 14.2 on end # Thermal Subsystem
device pci 15.0 on end # I2C Controller #0
device pci 15.1 on end # I2C Controller #1
device pci 15.2 off end # I2C Controller #2
device pci 15.3 off end # I2C Controller #3
device pci 16.0 off end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R
device pci 16.3 off end # Management Engine KT Redirection
device pci 16.4 off end # Management Engine Intel MEI #3
device pci 17.0 on end # SATA Controller
device pci 19.0 on end # UART Controller #2
device pci 19.1 off end # I2C Controller #5
device pci 19.2 on end # I2C Controller #4
device pci 1c.0 on end # PCI Express Port 1
device pci 1c.1 off end # PCI Express Port 2
device pci 1c.2 off end # PCI Express Port 3
device pci 1c.3 off end # PCI Express Port 4
device pci 1c.4 on end # PCI Express Port 5
device pci 1c.5 off end # PCI Express Port 6
device pci 1c.6 off end # PCI Express Port 7
device pci 1c.7 off end # PCI Express Port 8
device pci 1d.0 off end # PCI Express Port 9
device pci 1d.1 off end # PCI Express Port 10
device pci 1d.2 off end # PCI Express Port 11
device pci 1d.3 off end # PCI Express Port 12
device pci 1e.0 on end # UART #0
device pci 1e.1 off end # UART #1
device pci 1e.2 off end # GSPI #0
device pci 1e.3 off end # GSPI #1
device pci 1e.4 on end # eMMC
device pci 1e.6 on end # SDCard
device pci 1f.0 on
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end
chip ec/google/chromeec
device pnp 0c09.0 on end
end
end # LPC Interface
device pci 1f.2 on end # Power Management Controller
device pci 1f.3 on end # Intel High Definition Audio
device pci 1f.4 on end # SMBus Controller
device pci 1f.5 on end # PCH SPI
device pci 1f.6 off end # GbE Controller
end
end
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