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/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/cache.h>
#include <symbols.h>
#include <soc/soc_services.h>
#include "mmu.h"
#define WIFI_IMEM_0_START ((uintptr_t)_wifi_imem_0 / KiB)
#define WIFI_IMEM_0_END ((uintptr_t)_ewifi_imem_0 / KiB)
#define WIFI_IMEM_1_START ((uintptr_t)_wifi_imem_1 / KiB)
#define WIFI_IMEM_1_END ((uintptr_t)_ewifi_imem_1 / KiB)
#define DRAM_START ((uintptr_t)_dram / MiB)
#define DRAM_SIZE (CONFIG_DRAM_SIZE_MB)
#define DRAM_END (DRAM_START + DRAM_SIZE)
/* DMA memory for drivers */
#define DMA_START ((uintptr_t)_dma_coherent / MiB)
#define DMA_SIZE (_dma_coherent_size / MiB)
void setup_dram_mappings(enum dram_state dram)
{
if (dram == DRAM_INITIALIZED) {
mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK);
/* Map DMA memory */
mmu_config_range(DMA_START, DMA_SIZE, DCACHE_OFF);
/* Mark cbmem backing store as ready. */
ipq_cbmem_backing_store_ready();
} else {
mmu_disable_range(DRAM_START, DRAM_SIZE);
/* Map DMA memory */
mmu_disable_range(DMA_START, DMA_SIZE);
}
}
void setup_mmu(enum dram_state dram)
{
dcache_mmu_disable();
mmu_init();
/* start with mapping everything as strongly ordered. */
mmu_config_range(0, 4096, DCACHE_OFF);
/* Map Device memory. */
mmu_config_range_kb(WIFI_IMEM_0_START,
WIFI_IMEM_0_END - WIFI_IMEM_0_START,
DCACHE_WRITEBACK);
mmu_config_range_kb(WIFI_IMEM_1_START,
WIFI_IMEM_1_END - WIFI_IMEM_1_START,
DCACHE_WRITEBACK);
/* Map DRAM memory */
setup_dram_mappings(dram);
mmu_disable_range(DRAM_END, 4096 - DRAM_END);
/* disable Page 0 for trapping NULL pointer references. */
mmu_disable_range_kb(0, 1);
dcache_mmu_enable();
}
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