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/*
* This file is part of the coreboot project.
*
* Copyright 2020 The coreboot project Authors.
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#include <baseboard/gpio.h>
#include <baseboard/variants.h>
#include <commonlib/helpers.h>
#include <vendorcode/google/chromeos/chromeos.h>
/* Pad configuration in ramstage*/
static const struct pad_config gpio_table[] = {
/* GPP_A0 thru GPP_A6 come configured out of reset, do not touch */
/* A0 : ESPI_IO0 */
/* A1 : ESPI_IO1 */
/* A2 : ESPI_IO2 */
/* A3 : ESPI_IO3 */
/* A4 : ESPI_CS# */
/* A5 : ESPI_CLK */
/* A6 : ESPI_RESET_L */
};
/* Early pad configuration in bootblock */
static const struct pad_config early_gpio_table[] = {
/* ToDo: Fill early gpio configuration */
};
const struct pad_config *__weak variant_gpio_table(size_t *num)
{
*num = ARRAY_SIZE(gpio_table);
return gpio_table;
}
const struct pad_config *__weak variant_early_gpio_table(size_t *num)
{
*num = ARRAY_SIZE(early_gpio_table);
return early_gpio_table;
}
/* GPIO settings before entering sleep. */
static const struct pad_config sleep_gpio_table[] = {
};
const struct pad_config *__weak variant_sleep_gpio_table(size_t *num)
{
*num = ARRAY_SIZE(sleep_gpio_table);
return sleep_gpio_table;
}
static const struct cros_gpio cros_gpios[] = {
};
const struct cros_gpio *__weak variant_cros_gpios(size_t *num)
{
*num = ARRAY_SIZE(cros_gpios);
return cros_gpios;
}
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