aboutsummaryrefslogtreecommitdiff
path: root/src/mainboard/google/cyan/variants/celes/overridetree.cb
blob: 1eabd8e3153c0e2fc6aca647cb463c7f8edaf6c7 (plain) 
1
2
3
4
5
6
7
8

chip soc/intel/braswell

	register "PcdPchSsicEnable" = "0"
	register "PcdPchUsbHsicPort" = "0"

	device domain 0 on end

end
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-28 21:30:06 +0000