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## This file is part of the coreboot project.
## SPDX-License-Identifier: GPL-2.0-only
FLASH@0x0 8M {
WP_RO 4M {
RO_SECTION 0x184000 {
BOOTBLOCK 96K
COREBOOT(CBFS)
#TODO: Move FMAP to 2M or 3M once FSG can be smaller
FMAP@0x180000 0x1000
GBB 0x2f00
RO_FRID 0x100
}
RO_VPD(PRESERVE) 16K
RO_DDR_TRAINING(PRESERVE) 8K
RO_LIMITS_CFG(PRESERVE) 4K
RO_FSG(PRESERVE)
}
RW_VPD(PRESERVE) 32K
RW_NVRAM(PRESERVE) 16K
RW_DDR_TRAINING(PRESERVE) 8K
RW_LIMITS_CFG(PRESERVE) 4K
RW_ELOG(PRESERVE) 4K
RW_SHARED 4K {
SHARED_DATA
}
RW_SECTION_A 1280K {
VBLOCK_A 8K
FW_MAIN_A(CBFS)
RW_FWID_A 256
}
RW_SECTION_B 1280K {
VBLOCK_B 8K
FW_MAIN_B(CBFS)
RW_FWID_B 256
}
RW_LEGACY(CBFS)
}
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