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FLASH 32M {
SI_ALL 3776K {
SI_DESC 4K
SI_ME {
CSE_LAYOUT 8K
CSE_RO 1360K
CSE_DATA 420K
# 64-KiB aligned to optimize RW erases during CSE update.
CSE_RW 1984K
}
}
SI_BIOS 28992K {
RW_SECTION_A 4344K {
VBLOCK_A 8K
FW_MAIN_A(CBFS)
RW_FWID_A 64
ME_RW_A(CBFS) 1434K
}
RW_LEGACY(CBFS) 1M
RW_MISC 152K {
UNIFIED_MRC_CACHE(PRESERVE) 128K {
RECOVERY_MRC_CACHE 64K
RW_MRC_CACHE 64K
}
RW_ELOG(PRESERVE) 4K
RW_SHARED 4K {
SHARED_DATA 4K
}
RW_VPD(PRESERVE) 8K
RW_NVRAM(PRESERVE) 8K
}
# RW UNUSED Region 1.
RW_UNUSED_1 7088K
# This section starts at the 16M boundary in SPI flash.
# ADL does not support a region crossing this boundary,
# because the SPI flash is memory-mapped into two non-
# contiguous windows.
RW_SECTION_B 4344K {
VBLOCK_B 8K
FW_MAIN_B(CBFS)
RW_FWID_B 64
ME_RW_B(CBFS) 1434K
}
# RW UNUSED Region 2.
RW_UNUSED_2 7944K
# Make WP_RO region align with SPI vendor
# memory protected range specification.
WP_RO 4M {
RO_VPD(PRESERVE) 16K
RO_SECTION {
FMAP 2K
RO_FRID 64
GBB@4K 12K
COREBOOT(CBFS)
}
}
}
}
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