1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
|
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */
#include <arch/smp/mpspec.h>
#include <arch/ioapic.h>
#include <stdint.h>
#include <cpu/x86/lapic.h>
#include <southbridge/amd/common/amd_pci_util.h>
#include <drivers/generic/ioapic/chip.h>
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
/*
* By the time this function gets called, the IOAPIC registers
* have been written so they can be read to get the correct
* APIC ID and Version
*/
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
/* Initialize the MP_Table */
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
/*
* Type 0: Processor Entries:
* LAPIC ID, LAPIC Version, CPU Flags:EN/BP,
* CPU Signature (Stepping, Model, Family),
* Feature Flags
*/
smp_write_processors(mc);
/*
* Type 1: Bus Entries:
* Bus ID, Bus Type
*/
mptable_write_buses(mc, NULL, &bus_isa);
/*
* Type 2: I/O APICs:
* APIC ID, Version, APIC Flags:EN, Address
*/
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
/*
* Type 3: I/O Interrupt Table Entries:
* Int Type, Int Polarity, Int Level, Source Bus ID,
* Source Bus IRQ, Dest APIC ID, Dest PIN#
*/
mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
/* APU Internal Graphic Device */
PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]);
PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]);
/* SMBUS / ACPI */
PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]);
/* Southbridge HD Audio */
PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]);
/* LPC */
PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]);
/* USB */
PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]);
PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]);
PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]);
PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]);
PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[PIRQ_OHCI3]);
PCI_INT(0x0, 0x16, 0x2, intr_data_ptr[PIRQ_EHCI3]);
PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_OHCI4]);
/* SATA */
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]);
/* on board NIC & Slot PCIE */
PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]);
PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_F]);
/* PCI slots */
struct device *dev = pcidev_on_root(0x14, 4);
if (dev && dev->enabled) {
u8 bus_pci = dev->link_list->secondary;
/* PCI_SLOT 0 */
PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]);
PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]);
PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]);
PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]);
/* PCI_SLOT 1 */
PCI_INT(bus_pci, 0x6, 0x0, intr_data_ptr[PIRQ_F]);
PCI_INT(bus_pci, 0x6, 0x1, intr_data_ptr[PIRQ_G]);
PCI_INT(bus_pci, 0x6, 0x2, intr_data_ptr[PIRQ_H]);
PCI_INT(bus_pci, 0x6, 0x3, intr_data_ptr[PIRQ_E]);
/* PCI_SLOT 2 */
PCI_INT(bus_pci, 0x7, 0x0, intr_data_ptr[PIRQ_G]);
PCI_INT(bus_pci, 0x7, 0x1, intr_data_ptr[PIRQ_H]);
PCI_INT(bus_pci, 0x7, 0x2, intr_data_ptr[PIRQ_E]);
PCI_INT(bus_pci, 0x7, 0x3, intr_data_ptr[PIRQ_F]);
PCI_INT(bus_pci, 0x0, 0x0, intr_data_ptr[PIRQ_C]);
PCI_INT(bus_pci, 0x0, 0x1, intr_data_ptr[PIRQ_D]);
PCI_INT(bus_pci, 0x0, 0x2, intr_data_ptr[PIRQ_E]);
}
/* PCIe Lan*/
PCI_INT(0x0, 0x06, 0x0, intr_data_ptr[PIRQ_D]);
/* FCH PCIe PortA */
PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_A]);
/* FCH PCIe PortB */
PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_B]);
/* FCH PCIe PortC */
PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_C]);
/* FCH PCIe PortD */
PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_D]);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
/* Compute the checksums */
return mptable_finalize(mc);
}
unsigned long write_smp_table(unsigned long addr)
{
void *v;
v = smp_write_floating_table(addr, 0);
return (unsigned long)smp_write_config_table(v);
}
|
