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##
## This file is part of the coreboot project.
##
##
## SPDX-License-Identifier: GPL-2.0-only
# To execute, do:
# util/riscv/make-spike-elf.sh build/coreboot.rom build/coreboot.elf
# qemu-system-riscv64 -M virt -m 1024M -nographic -kernel build/coreboot.elf
if BOARD_EMULATION_QEMU_RISCV_RV64
config BOARD_EMULATION_QEMU_RISCV
def_bool y
select ARCH_RISCV_RV64
endif
if BOARD_EMULATION_QEMU_RISCV_RV32
config BOARD_EMULATION_QEMU_RISCV
def_bool y
select ARCH_RISCV_RV32
endif
if BOARD_EMULATION_QEMU_RISCV
config BOARD_SPECIFIC_OPTIONS
def_bool y
select SOC_UCB_RISCV
select BOARD_ROMSIZE_KB_4096
select BOOT_DEVICE_NOT_SPI_FLASH
select MISSING_BOARD_RESET
select DRIVERS_UART_8250MEM
select RISCV_HAS_OPENSBI
config MAINBOARD_DIR
string
default "emulation/qemu-riscv"
config MAINBOARD_PART_NUMBER
string
default "QEMU RISCV"
config MAX_CPUS
int
default 1
config DRAM_SIZE_MB
int
default 32768
config OPENSBI_PLATFORM
string
default "qemu/virt"
# ugly, but CBFS is placed in DRAM...
config OPENSBI_TEXT_START
hex
default 0x80010000 if COREBOOT_ROMSIZE_KB_64
default 0x80020000 if COREBOOT_ROMSIZE_KB_128
default 0x80040000 if COREBOOT_ROMSIZE_KB_256
default 0x80080000 if COREBOOT_ROMSIZE_KB_512
default 0x80100000 if COREBOOT_ROMSIZE_KB_1024
default 0x80200000 if COREBOOT_ROMSIZE_KB_2048
default 0x80400000 if COREBOOT_ROMSIZE_KB_4096
default 0x80600000 if COREBOOT_ROMSIZE_KB_6144
default 0x80800000 if COREBOOT_ROMSIZE_KB_8192
default 0x80a00000 if COREBOOT_ROMSIZE_KB_10240
default 0x80c00000 if COREBOOT_ROMSIZE_KB_12288
default 0x81000000 if COREBOOT_ROMSIZE_KB_16384
default 0x82000000 if COREBOOT_ROMSIZE_KB_32768
default 0x84000000 if COREBOOT_ROMSIZE_KB_65536
endif # BOARD_EMULATION_QEMU_RISCV
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