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chip northbridge/amd/lx
device pci_domain 0 on
device pci 1.0 on end # Northbridge
device pci 1.1 on end # Graphics
device pci 1.2 on end # AES
chip southbridge/amd/cs5536
register "lpc_serirq_enable" = "0x00000000"
register "lpc_serirq_polarity" = "0x00000000"
register "lpc_serirq_mode" = "0"
register "enable_gpio_int_route" = "0x0C0D0700"
register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
register "enable_USBP4_device" = "0" #0: host, 1:device
register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
register "com1_enable" = "1"
register "com1_address" = "0x3F8"
register "com1_irq" = "4"
register "com2_enable" = "1"
register "com2_address" = "0x2F8"
register "com2_irq" = "3"
register "unwanted_vpci[0]" = "0" # End of list has a zero
device pci 4.0 on end # Ethernet 0
device pci f.0 on end # ISA Bridge
device pci f.2 on end # IDE Controller
device pci f.3 on end # Audio
device pci f.4 on end # OHCI
device pci f.5 on end # EHCI
device pci f.7 on end # UOC
end
end
# APIC cluster is late CPU init.
device lapic_cluster 0 on
chip cpu/amd/geode_lx
device lapic 0 on end
end
end
end
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