blob: 075388e20a67d3395e2f04e00a7104e413005c25 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
|
##
## This file is part of the coreboot project.
##
## Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
## Copyright (C) 2007 AMD
## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
entries
0 384 r 0 reserved_memory
384 1 e 4 boot_option
388 4 r 0 reboot_bits
393 3 e 5 baud_rate
396 5 e 10 ecc_scrub_rate
401 1 e 1 interleave_chip_selects
402 1 e 1 interleave_nodes
403 1 e 1 interleave_memory_channels
404 4 e 8 max_mem_clock
408 1 e 2 multi_core
412 4 e 6 debug_level
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 gart
446 2 e 3 power_on_after_fail
456 1 e 1 ECC_memory
457 1 e 1 ECC_redirection
458 4 e 11 hypertransport_speed_limit
462 2 e 12 minimum_memory_voltage
464 1 e 2 compute_unit_siblings
465 1 e 1 cpu_c_states
466 1 e 1 cpu_cc6_state
467 1 e 1 sata_ahci_mode
468 1 e 1 sata_alpm
469 4 h 0 maximum_p_state_limit
473 2 e 13 dimm_spd_checksum
475 1 e 14 probe_filter
476 1 e 1 l3_cache_partitioning
477 1 e 1 ieee1394_controller
478 1 e 1 iommu
479 1 e 1 cpu_core_boost
480 1 e 1 experimental_memory_speed_boost
481 1 r 0 allow_spd_nvram_cache_restore
728 256 h 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 amd_reserved
enumerations
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
3 0 Off
3 1 On
3 2 Last
4 0 Fallback
4 1 Normal
5 0 115200
5 1 57600
5 2 38400
5 3 19200
5 4 9600
5 5 4800
5 6 2400
5 7 1200
6 0 Emergency
6 1 Alert
6 2 Critical
6 3 Error
6 4 Warning
6 5 Notice
6 6 Information
6 7 Debug
6 8 Spew
8 0 DDR3-1866
8 1 DDR3-1600
8 2 DDR3-1333
8 3 DDR3-1066
8 4 DDR3-800
8 5 DDR3-667
9 0 off
9 1 87.5%
9 2 75.0%
9 3 62.5%
9 4 50.0%
9 5 37.5%
9 6 25.0%
9 7 12.5%
10 0 Disabled
10 1 40ns
10 2 80ns
10 3 160ns
10 4 320ns
10 5 640ns
10 6 1.28us
10 7 2.56us
10 8 5.12us
10 9 10.2us
10 10 20.5us
10 11 41us
10 12 81.9us
10 13 163.8us
10 14 327.7us
10 15 655.4us
10 16 1.31ms
10 17 2.62ms
10 18 5.24ms
10 19 10.49ms
10 20 20.97ms
10 21 42ms
10 22 84ms
11 0 Auto
11 1 3.2GHz
11 2 3.0GHz
11 3 2.8GHz
11 4 2.6GHz
11 5 2.4GHz
11 6 2.2GHz
11 7 2.0GHz
11 8 1.8GHz
11 9 1.6GHz
11 10 1.4GHz
11 11 1.2GHz
11 12 1.0GHz
11 13 800MHz
11 14 600MHz
11 15 500MHz
12 0 1.5V
12 1 1.35V
12 2 1.25V
12 3 1.15V
13 0 Enforce
13 1 Ignore
13 2 Override
14 0 Disable
14 1 Auto
checksums
checksum 392 983 984
|
