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/* SPDX-License-Identifier: GPL-2.0-only */
#include <gpio.h>
#include <mainboard/gpio.h>
/*
* Pad configuration was generated automatically using intelp2m utility
* [*] - allow FSP to configure this pad
*/
static const struct pad_config gpio_table[] = {
/* ------- GPIO Community 0 ------- */
/* ------- GPIO Group GPP_A ------- */
PAD_CFG_NF(GPP_A0, NONE, PLTRST, NF1), /* RCIN# */
PAD_CFG_NF(GPP_A1, NONE, PLTRST, NF1), /* LAD0 */
PAD_CFG_NF(GPP_A2, NONE, PLTRST, NF1), /* LAD1 */
PAD_CFG_NF(GPP_A3, NONE, PLTRST, NF1), /* LAD2 */
PAD_CFG_NF(GPP_A4, NONE, PLTRST, NF1), /* LAD3 */
PAD_CFG_NF(GPP_A5, NONE, PLTRST, NF1), /* LFRAME# */
PAD_CFG_NF(GPP_A6, NONE, PLTRST, NF1), /* SERIRQ */
PAD_CFG_NF(GPP_A7, NONE, PLTRST, NF1), /* PIRQA# */
PAD_CFG_NF(GPP_A8, NONE, PLTRST, NF1), /* CLKRUN# */
PAD_CFG_NF(GPP_A9, NONE, PLTRST, NF1), /* CLKOUT_LPC0 */
PAD_CFG_NF(GPP_A10, NONE, PLTRST, NF1), /* CLKOUT_LPC1 */
PAD_CFG_NF(GPP_A11, NONE, PLTRST, NF1), /* PME# */
PAD_NC(GPP_A12, NONE),
PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* SUSWARN#/SUSPWRDNACK */
PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), /* SUS_STAT# */
PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), /* SUSACK# */
PAD_CFG_NF(GPP_A16, NONE, PLTRST, NF1), /* CLKOUT_48 */
PAD_NC(GPP_A17, NONE),
PAD_NC(GPP_A18, NONE),
PAD_NC(GPP_A19, NONE),
PAD_NC(GPP_A20, NONE),
PAD_NC(GPP_A21, NONE),
PAD_NC(GPP_A22, NONE),
PAD_NC(GPP_A23, NONE),
/* ------- GPIO Group GPP_B ------- */
PAD_NC(GPP_B0, NONE),
PAD_CFG_GPO(GPP_B1, 1, PLTRST), /* GPIO */
PAD_NC(GPP_B2, NONE),
PAD_NC(GPP_B3, NONE),
PAD_NC(GPP_B4, NONE),
/* [*] GPP_B5 GPIO/SRCCLKREQ0# */
/* [*] GPP_B6 GPIO/SRCCLKREQ1# */
/* [*] GPP_B7 GPIO/SRCCLKREQ2# */
/* [*] GPP_B8 GPIO/SRCCLKREQ3# */
/* [*] GPP_B9 GPIO/SRCCLKREQ4# */
/* [*] GPP_B10 GPIO/SRCCLKREQ5# */
PAD_NC(GPP_B11, NONE),
PAD_NC(GPP_B12, NONE),
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PLTRST# */
PAD_CFG_NF(GPP_B14, DN_20K, PLTRST, NF1), /* SPKR */
PAD_NC(GPP_B15, NONE),
PAD_NC(GPP_B16, NONE),
PAD_NC(GPP_B17, NONE),
PAD_CFG_GPO(GPP_B18, 0, PLTRST),
PAD_NC(GPP_B19, NONE),
PAD_NC(GPP_B20, NONE),
PAD_NC(GPP_B21, NONE),
PAD_CFG_GPO(GPP_B22, 0, PLTRST),
PAD_CFG_GPO(GPP_B23, 0, PLTRST),
/* ------- GPIO Community 1 ------- */
/* ------- GPIO Group GPP_C ------- */
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMBCLK */
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMBDATA */
PAD_CFG_GPO(GPP_C2, 1, PLTRST), /* GPIO */
PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* SML0CLK */
PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* SML0DATA */
PAD_CFG_GPO(GPP_C5, 0, PLTRST), /* GPIO */
PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* SML1CLK */
PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* SML1DATA */
PAD_NC(GPP_C8, NONE),
PAD_NC(GPP_C9, NONE),
PAD_NC(GPP_C10, NONE),
PAD_NC(GPP_C11, NONE),
PAD_NC(GPP_C12, NONE),
PAD_NC(GPP_C13, NONE),
PAD_NC(GPP_C14, NONE),
PAD_NC(GPP_C15, NONE),
PAD_NC(GPP_C16, NONE),
PAD_NC(GPP_C17, NONE),
PAD_NC(GPP_C18, NONE),
PAD_NC(GPP_C19, NONE),
PAD_NC(GPP_C20, NONE),
PAD_NC(GPP_C21, NONE),
PAD_NC(GPP_C22, NONE),
PAD_NC(GPP_C23, NONE),
/* ------- GPIO Group GPP_D ------- */
PAD_NC(GPP_D0, NONE),
PAD_NC(GPP_D1, NONE),
PAD_NC(GPP_D2, NONE),
PAD_NC(GPP_D3, NONE),
PAD_NC(GPP_D4, NONE),
PAD_CFG_NF(GPP_D5, NONE, PLTRST, NF3), /* CNV_RF_RESET# */
PAD_CFG_NF(GPP_D6, NONE, PLTRST, NF3), /* MODEM_CLKREQ */
PAD_CFG_NF(GPP_D7, NONE, PLTRST, NF1), /* I2S2_RXD */
PAD_CFG_NF(GPP_D8, NONE, PLTRST, NF1), /* I2S2_SCLK */
PAD_NC(GPP_D9, NONE),
PAD_NC(GPP_D10, NONE),
PAD_NC(GPP_D11, NONE),
PAD_NC(GPP_D12, NONE),
PAD_NC(GPP_D13, NONE),
PAD_NC(GPP_D14, NONE),
PAD_CFG_NF(GPP_D15, NONE, PLTRST, NF4), /* CNV_WFEN */
PAD_CFG_NF(GPP_D16, NONE, PLTRST, NF4), /* CNV_WCEN */
PAD_CFG_NF(GPP_D17, NONE, PLTRST, NF1), /* DMIC_CLK1 */
PAD_CFG_NF(GPP_D18, NONE, PLTRST, NF1), /* DMIC_DATA1 */
PAD_CFG_NF(GPP_D19, NONE, PLTRST, NF1), /* DMIC_CLK0 */
PAD_CFG_NF(GPP_D20, NONE, PLTRST, NF1), /* DMIC_DATA0 */
PAD_NC(GPP_D21, NONE),
PAD_NC(GPP_D22, NONE),
PAD_NC(GPP_D23, NONE),
/* ------- GPIO Group GPP_G ------- */
PAD_CFG_GPI_TRIG_OWN(GPP_G0, NONE, DEEP, OFF, ACPI), /* GPIO */
PAD_CFG_GPO(GPP_G1, 1, DEEP), /* GPIO */
PAD_CFG_GPO(GPP_G2, 1, DEEP), /* GPIO */
PAD_CFG_GPO(GPP_G3, 1, DEEP), /* GPIO */
PAD_CFG_GPO(GPP_G4, 1, DEEP), /* GPIO */
PAD_CFG_GPO(GPP_G5, 1, DEEP), /* GPIO */
PAD_NC(GPP_G6, NONE),
PAD_NC(GPP_G7, NONE),
/* ------- GPIO Community 2 ------- */
/* ------- GPIO Group GPD ------- */
PAD_CFG_NF(GPD0, NONE, RSMRST, NF1), /* BATLOW# */
PAD_CFG_NF(GPD1, NONE, RSMRST, NF1), /* ACPRESENT */
PAD_CFG_NF(GPD2, NONE, RSMRST, NF1), /* LAN_WAKE# */
PAD_CFG_NF(GPD3, NONE, RSMRST, NF1), /* PRWBTN# */
PAD_CFG_NF(GPD4, NONE, RSMRST, NF1), /* SLP_S3# */
PAD_CFG_NF(GPD5, NONE, RSMRST, NF1), /* SLP_S4# */
PAD_CFG_NF(GPD6, NONE, RSMRST, NF1), /* SLP_A# */
PAD_CFG_GPO(GPD7, 1, PLTRST), /* GPIO */
PAD_CFG_NF(GPD8, NONE, RSMRST, NF1), /* SUSCLK */
PAD_CFG_NF(GPD9, NONE, RSMRST, NF1), /* SLP_WLAN# */
PAD_CFG_NF(GPD10, NONE, RSMRST, NF1), /* SLP_S5# */
PAD_CFG_NF(GPD11, NONE, RSMRST, NF1), /* LANPHYPC */
/* ------- GPIO Community 3 ------- */
/* ------- GPIO Group GPP_K ------- */
PAD_CFG_GPO(GPP_K0, 0, PLTRST), /* GPIO */
PAD_CFG_GPO(GPP_K1, 0, PLTRST), /* GPIO */
PAD_CFG_GPO(GPP_K2, 0, PLTRST), /* GPIO */
PAD_CFG_GPO(GPP_K3, 0, PLTRST), /* GPIO */
PAD_CFG_GPO(GPP_K4, 1, PLTRST), /* GPIO */
PAD_CFG_GPO(GPP_K5, 1, PLTRST), /* GPIO */
PAD_NC(GPP_K6, NONE),
PAD_NC(GPP_K7, NONE),
PAD_CFG_GPO(GPP_K8, 0, PLTRST), /* GPIO */
PAD_CFG_GPO(GPP_K9, 0, PLTRST), /* GPIO */
PAD_CFG_GPO(GPP_K10, 0, PLTRST), /* GPIO */
PAD_CFG_GPO(GPP_K11, 0, PLTRST), /* GPIO */
PAD_CFG_GPI_SCI(GPP_K12, NONE, PLTRST, EDGE_SINGLE, INVERT), /* GPIO */
PAD_NC(GPP_K13, NONE), /* GPIO */
PAD_CFG_GPO(GPP_K14, 0, DEEP), /* GPIO */
PAD_CFG_GPI_TRIG_OWN(GPP_K15, NONE, PLTRST, OFF, ACPI), /* GPIO */
PAD_CFG_GPO(GPP_K16, 0, PLTRST), /* GPIO */
PAD_CFG_GPI_TRIG_OWN(GPP_K17, NONE, PLTRST, OFF, ACPI), /* GPIO */
PAD_NC(GPP_K18, NONE),
PAD_NC(GPP_K19, NONE),
PAD_CFG_GPI_TRIG_OWN(GPP_K20, NONE, PLTRST, OFF, ACPI), /* GPIO */
PAD_CFG_GPI_TRIG_OWN(GPP_K21, NONE, DEEP, OFF, ACPI), /* GPIO */
PAD_CFG_GPI_TRIG_OWN(GPP_K22, NONE, PLTRST, OFF, ACPI), /* GPIO */
PAD_CFG_GPI_TRIG_OWN(GPP_K23, NONE, PLTRST, OFF, ACPI), /* GPIO */
/* ------- GPIO Group GPP_H ------- */
/* [*] GPP_H0 GPIO/SRCCLKREQ6# */
/* [*] GPP_H1 GPIO/SRCCLKREQ7# */
PAD_NC(GPP_H2, NONE),
PAD_NC(GPP_H3, NONE),
PAD_NC(GPP_H4, NONE),
PAD_NC(GPP_H5, NONE),
PAD_NC(GPP_H6, NONE),
PAD_NC(GPP_H7, NONE),
PAD_NC(GPP_H8, NONE),
PAD_NC(GPP_H9, NONE),
PAD_NC(GPP_H10, NONE),
PAD_NC(GPP_H11, NONE),
PAD_CFG_GPO(GPP_H12, 0, PLTRST), /* GPIO */
PAD_NC(GPP_H13, NONE),
PAD_NC(GPP_H14, NONE),
PAD_NC(GPP_H15, NONE),
PAD_NC(GPP_H16, NONE),
PAD_NC(GPP_H17, NONE),
PAD_NC(GPP_H18, NONE),
PAD_NC(GPP_H19, NONE),
PAD_NC(GPP_H20, NONE),
PAD_NC(GPP_H21, NONE),
PAD_NC(GPP_H22, NONE),
PAD_NC(GPP_H23, NONE),
/* ------- GPIO Group GPP_E ------- */
PAD_CFG_NF(GPP_E0, NONE, PLTRST, NF1), /* SATAXPCIE0 */
PAD_CFG_NF(GPP_E1, NONE, PLTRST, NF1), /* SATAXPCIE1 */
PAD_CFG_NF(GPP_E2, NONE, PLTRST, NF1), /* SATAXPCIE2 */
PAD_CFG_GPO(GPP_E3, 1, PLTRST), /* GPIO */
PAD_NC(GPP_E4, NONE),
PAD_CFG_GPI_SMI(GPP_E5, NONE, PLTRST, EDGE_SINGLE, INVERT), /* GPIO */
PAD_CFG_GPI_SMI(GPP_E6, NONE, PLTRST, EDGE_SINGLE, INVERT), /* GPIO */
PAD_NC(GPP_E7, NONE),
PAD_CFG_NF(GPP_E8, UP_5K, PLTRST, NF1), /* SATALED# */
PAD_NC(GPP_E9, NONE),
PAD_NC(GPP_E10, NONE),
PAD_NC(GPP_E11, NONE),
PAD_NC(GPP_E12, NONE),
/* ------- GPIO Group GPP_F ------- */
PAD_CFG_GPO(GPP_F0, 0, PLTRST), /* GPIO */
PAD_CFG_NF(GPP_F1, UP_5K, PLTRST, NF1), /* SATAXPCIE4 */
PAD_CFG_GPO(GPP_F2, 0, PLTRST), /* GPIO */
PAD_CFG_GPO(GPP_F3, 0, PLTRST), /* GPIO */
PAD_CFG_GPO(GPP_F4, 0, PLTRST), /* GPIO */
PAD_NC(GPP_F5, NONE),
PAD_NC(GPP_F6, NONE),
PAD_NC(GPP_F7, NONE),
PAD_CFG_NF(GPP_F8, NONE, PLTRST, NF1), /* SATA_DEVSLP6 */
PAD_NC(GPP_F9, NONE),
PAD_NC(GPP_F10, NONE),
PAD_NC(GPP_F11, NONE),
PAD_NC(GPP_F12, NONE),
PAD_NC(GPP_F13, NONE),
PAD_CFG_NF(GPP_F14, NONE, PLTRST, NF2), /* PS_ON# */
PAD_NC(GPP_F15, NONE),
PAD_NC(GPP_F16, NONE),
PAD_NC(GPP_F17, NONE),
PAD_NC(GPP_F18, NONE),
PAD_CFG_NF(GPP_F19, NONE, PLTRST, NF1), /* eDP_VDDEN */
PAD_CFG_NF(GPP_F20, NONE, PLTRST, NF1), /* eDP_BKLTEN */
PAD_CFG_NF(GPP_F21, NONE, PLTRST, NF1), /* eDP_BKLTCTL */
PAD_NC(GPP_F22, NONE),
PAD_CFG_GPO(GPP_F23, 0, PLTRST), /* GPIO */
/* ------- GPIO Community 4 ------- */
/* ------- GPIO Group GPP_I ------- */
PAD_CFG_NF(GPP_I0, NONE, PLTRST, NF1), /* DDPB_HPD0 */
PAD_CFG_NF(GPP_I1, NONE, PLTRST, NF1), /* DDPB_HPD1 */
PAD_CFG_NF(GPP_I2, NONE, PLTRST, NF1), /* DDPB_HPD2 */
PAD_NC(GPP_I3, NONE),
PAD_CFG_NF(GPP_I4, NONE, PLTRST, NF1), /* EDP_HPD */
PAD_CFG_NF(GPP_I5, NONE, PLTRST, NF1), /* DDPB_CTRLCLK */
PAD_CFG_NF(GPP_I6, NONE, PLTRST, NF1), /* DDPB_CTRLDATA */
PAD_CFG_NF(GPP_I7, NONE, PLTRST, NF1), /* DDPC_CTRLCLK */
PAD_CFG_NF(GPP_I8, NONE, PLTRST, NF1), /* DDPC_CTRLDATA */
PAD_CFG_NF(GPP_I9, NONE, PLTRST, NF1), /* DDPD_CTRLCLK */
PAD_CFG_NF(GPP_I10, NONE, PLTRST, NF1), /* DDPD_CTRLDATA */
PAD_NC(GPP_I11, NONE),
PAD_CFG_GPO(GPP_I12, 1, PLTRST), /* GPIO */
PAD_NC(GPP_I13, NONE),
PAD_CFG_GPO(GPP_I14, 1, PLTRST), /* GPIO */
/* ------- GPIO Group GPP_J ------- */
PAD_CFG_NF(GPP_J0, NONE, PLTRST, NF1), /* CNV_PA_BLANKING */
PAD_CFG_NF(GPP_J1, NONE, PLTRST, NF2), /* CPU_C10_GATE# */
PAD_NC(GPP_J2, NONE),
PAD_NC(GPP_J3, NONE),
PAD_CFG_NF(GPP_J4, NONE, PLTRST, NF1), /* CNV_BRI_DT */
PAD_CFG_NF(GPP_J5, NONE, PLTRST, NF1), /* CNV_BRI_RSP */
PAD_CFG_NF(GPP_J6, NONE, PLTRST, NF1), /* CNV_RGI_DT */
PAD_CFG_NF(GPP_J7, NONE, PLTRST, NF1), /* CNV_RGI_RSP */
PAD_CFG_NF(GPP_J8, NONE, PLTRST, NF1), /* CNV_MFUART2_RXD */
PAD_CFG_NF(GPP_J9, NONE, PLTRST, NF1), /* CNV_MFUART2_TXD */
PAD_NC(GPP_J10, NONE),
PAD_NC(GPP_J11, NONE),
};
void mainboard_configure_gpios(void)
{
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
}
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