blob: 777d846cc01bf78a7c71a8f143f12e3eca859b63 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
|
config BOARD_AMD_SERENGETI_CHEETAH_FAM10
bool "Serengeti Cheetah (Fam10)"
select ARCH_X86
select CPU_AMD_SOCKET_F_1207
select NORTHBRIDGE_AMD_AMDFAM10
select NORTHBRIDGE_AMD_AMDFAM10_ROOT_COMPLEX
select SOUTHBRIDGE_AMD_AMD8111
select SOUTHBRIDGE_AMD_AMD8132
select SUPERIO_WINBOND_W83627HF
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select USE_PRINTK_IN_CAR
select USE_DCACHE_RAM
select HAVE_HARD_RESET
select IOAPIC
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
select SERIAL_CPU_INIT
select AMDMCT
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_1024
select ENABLE_APIC_EXT_ID
select LIFT_BSP_APIC_ID
select TINY_BOOTBLOCK
config MAINBOARD_DIR
string
default amd/serengeti_cheetah_fam10
depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
config APIC_ID_OFFSET
hex
default 0x0
depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
config LB_CKS_RANGE_END
int
default 122
depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
config LB_CKS_LOC
int
default 123
depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
config MAINBOARD_PART_NUMBER
string
default "Serengeti Cheetah (Fam10)"
depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
config HW_MEM_HOLE_SIZEK
hex
default 0x100000
depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
# 6 * MAX_PHYSICAL_CPUS
config MAX_CPUS
int
default 48
depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
config MAX_PHYSICAL_CPUS
int
default 8
depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
config HW_MEM_HOLE_SIZE_AUTO_INC
bool
default n
depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
config MEM_TRAIN_SEQ
int
default 2
depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
config SB_HT_CHAIN_ON_BUS0
int
default 2
depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
config HT_CHAIN_END_UNITID_BASE
hex
default 0x6
depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
config HT_CHAIN_UNITID_BASE
hex
default 0xa
depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
config USE_INIT
bool
default n
depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
config IRQ_SLOT_COUNT
int
default 11
depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
config AMD_UCODE_PATCH_FILE
string
default "mc_patch_01000095.h"
depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
config RAMTOP
hex
default 0x1000000
depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
config HEAP_SIZE
hex
default 0xc0000
depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
config ACPI_SSDTX_NUM
int
default 31
depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
hex
default 0x2b80
depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
hex
default 0x1022
depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
config RAMBASE
hex
default 0x200000
depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
config ID_SECTION_OFFSET
hex
default 0x80
depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
|
