1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
|
/* SPDX-License-Identifier: GPL-2.0-only */
/* DefinitionBlock Statement */
#include <acpi/acpi.h>
DefinitionBlock (
"dsdt.aml",
"DSDT",
ACPI_DSDT_REV_2,
OEM_ID,
ACPI_TABLE_CREATOR,
0x00010001 /* OEM Revision */
)
{ /* Start of ASL file */
#include <acpi/dsdt_top.asl>
/* global NVS and variables */
#include <globalnvs.asl>
/* Describe the USB Overcurrent pins */
#include "acpi/usb_oc.asl"
/* PCI IRQ mapping for the Southbridge */
#include <pcie.asl>
/* Describe the processor tree (\_SB) */
#include <cpu.asl>
/* Contains the supported sleep states for this chipset */
#include <sleepstates.asl>
/* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
#include "acpi/sleep.asl"
/* System Bus */
Scope(\_SB) { /* Start \_SB scope */
/* global utility methods expected within the \_SB scope */
#include <arch/x86/acpi/globutil.asl>
/* IRQ Routing mapping for this platform (in \_SB scope) */
#include "acpi/routing.asl"
Device(PWRB) {
Name(_HID, EISAID("PNP0C0C"))
Name(_UID, 0xAA)
Name(_PRW, Package () {3, 0x04})
Name(_STA, 0x0B)
}
/* Describe the SOC */
#include <soc.asl>
/* Describe the Fintek F81803A SIO */
#define SUPERIO_DEV SIO0
#define SUPERIO_PNP_BASE 0x4E
#define F81803A_SHOW_UARTA
#define F81803A_SHOW_PME
#include <superio/fintek/f81803a/acpi/superio.asl>
} /* End \_SB scope */
/* Define the General Purpose Events for the platform */
#include "acpi/gpe.asl"
}
/* End of ASL file */
|
