1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
|
chip soc/amd/genoa
# USB configuration
register "usb.xhci0_enable" = "1"
register "usb.xhci1_enable" = "1"
# OC pins
register "usb.usb2_oc_pins[0].port0" = "0x0"
register "usb.usb2_oc_pins[0].port1" = "0x1"
register "usb.usb2_oc_pins[0].port2" = "0x0"
register "usb.usb2_oc_pins[0].port3" = "0x1"
register "usb.usb2_oc_pins[1].port0" = "0x0"
register "usb.usb2_oc_pins[1].port1" = "0x1"
register "usb.usb3_oc_pins[0].port0" = "0x0"
register "usb.usb3_oc_pins[0].port1" = "0x1"
register "usb.usb3_oc_pins[0].port2" = "0x0"
register "usb.usb3_oc_pins[0].port3" = "0x1"
register "usb.usb3_oc_pins[1].port0" = "0x0"
register "usb.usb3_oc_pins[1].port1" = "0x1"
register "usb.polarity_cfg_low" = "true"
register "usb.usb3_force_gen1.port0" = "3"
register "usb.usb3_force_gen1.port1" = "3"
register "usb.usb3_force_gen1.port2" = "3"
register "usb.usb3_force_gen1.port3" = "3"
# eSPI configuration
register "common_config.espi_config" = "{
.std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN,
.io_mode = ESPI_IO_MODE_SINGLE,
.op_freq_mhz = ESPI_OP_FREQ_33_MHZ,
.crc_check_enable = 1,
.alert_pin = ESPI_ALERT_PIN_PUSH_PULL,
.periph_ch_en = 0,
.vw_ch_en = 0,
.oob_ch_en = 0,
.flash_ch_en = 0,
}"
# PHY settings
register "usb.usb31_phy_enable" = "1"
register "usb.usb31_phy" = "{
{0x01, 0x07, 0x00, 0x00, 0x07, 0x01, 0x05, 0x00, 0x05, 0x00, 0x05, 0x00},
{0x05, 0x07, 0x00, 0x00, 0x07, 0x01, 0x05, 0x00, 0x05, 0x00, 0x05, 0x00},
{0x05, 0x07, 0x00, 0x00, 0x07, 0x01, 0x05, 0x00, 0x05, 0x00, 0x05, 0x00},
{0x05, 0x07, 0x00, 0x00, 0x07, 0x01, 0x05, 0x00, 0x05, 0x00, 0x05, 0x00},
{0x05, 0x01, 0x07, 0x00, 0x00, 0x07, 0x01, 0x05, 0x00, 0x05, 0x00, 0x05},
{0x00, 0x05, 0x07, 0x00, 0x00, 0x07, 0x01, 0x05, 0x00, 0x05, 0x00, 0x05},
{0x00, 0x05, 0x07, 0x00, 0x00, 0x07, 0x01, 0x05, 0x00, 0x05, 0x00, 0x05},
{0x00, 0x05, 0x07, 0x00, 0x00, 0x07, 0x01, 0x05, 0x00, 0x05, 0x00, 0x05},
}"
device domain 0 on
end
end
|
