blob: f406f9f3b427389e7954c9ed479b102b098ecdaf (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
|
/* SPDX-License-Identifier: GPL-2.0-only */
#include <memlayout.h>
/* This file is included inside a SECTIONS block */
/* First we place the code and read only data (typically const declared).
* This could theoretically be placed in rom.
* The '.' in '.text . : {' is actually significant to prevent missing some
* SoC's entry points due to artificial alignment restrictions, see
* https://sourceware.org/binutils/docs/ld/Output-Section-Address.html
*/
.text . : {
_program = .;
_text = .;
#if !(ENV_X86 && ENV_BOOTBLOCK)
*(.init._start);
*(.init);
*(.init.*);
#endif
*(.text._start);
*(.text.stage_entry);
KEEP(*(.metadata_hash_anchor));
*(.text);
*(.text.*);
#if ENV_HAS_CBMEM
. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
_cbmem_init_hooks = .;
KEEP(*(.rodata.cbmem_init_hooks_early));
KEEP(*(.rodata.cbmem_init_hooks));
_ecbmem_init_hooks = .;
RECORD_SIZE(cbmem_init_hooks)
#endif
. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
_rsbe_init_begin = .;
KEEP(*(.rsbe_init));
_ersbe_init_begin = .;
RECORD_SIZE(rsbe_init_begin)
#if ENV_RAMSTAGE
. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
_pci_drivers = .;
KEEP(*(.rodata.pci_driver));
_epci_drivers = .;
RECORD_SIZE(pci_drivers)
. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
_cpu_drivers = .;
KEEP(*(.rodata.cpu_driver));
_ecpu_drivers = .;
RECORD_SIZE(cpu_drivers)
#endif
. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
*(.rodata);
*(.rodata.*);
. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
_etext = .;
RECORD_SIZE(text)
} : to_load
#if ENV_RAMSTAGE && (CONFIG(COVERAGE) || CONFIG(ASAN_IN_RAMSTAGE))
.ctors . : {
. = ALIGN(0x100);
__CTOR_LIST__ = .;
KEEP(*(.ctors));
LONG(0);
LONG(0);
__CTOR_END__ = .;
}
#endif
/* Include data, bss, and heap in that order. Not defined for all stages. */
#if !ENV_SEPARATE_DATA_AND_BSS
.data . : {
. = ALIGN(ARCH_CACHELINE_ALIGN_SIZE);
_data = .;
/*
* The postcar phase uses a stack value that is located in the relocatable
* module section. While the postcar stage could be linked like smm and
* other rmodules the postcar stage needs similar semantics of the more
* traditional stages in the coreboot infrastructure. Therefore it's easier
* to specialize this case.
*/
#if ENV_RMODULE || ENV_POSTCAR
_rmodule_params = .;
KEEP(*(.module_parameters));
_ermodule_params = .;
RECORD_SIZE(rmodule_params)
#endif
*(.data);
*(.data.*);
*(.sdata);
*(.sdata.*);
#if ENV_ROMSTAGE_OR_BEFORE
PROVIDE(_preram_cbmem_console = .);
PROVIDE(_epreram_cbmem_console = _preram_cbmem_console);
PROVIDE(_preram_cbmem_console_size = ABSOLUTE(0));
#elif ENV_RAMSTAGE
. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
_bs_init_begin = .;
KEEP(*(.bs_init));
LONG(0);
LONG(0);
_ebs_init_begin = .;
RECORD_SIZE(bs_init_begin)
#endif
. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
_edata = .;
RECORD_SIZE(data)
}
#endif
#if !ENV_SEPARATE_DATA_AND_BSS
.bss . : {
. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
_bss = .;
*(.bss)
*(.bss.*)
*(.sbss)
*(.sbss.*)
. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
_ebss = .;
RECORD_SIZE(bss)
}
#endif
#if ENV_HAS_HEAP_SECTION
.heap . : {
. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
_heap = .;
. += (ENV_RMODULE ? __heap_size : CONFIG_HEAP_SIZE);
. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
_eheap = .;
RECORD_SIZE(heap)
}
#endif
#if ENV_RAMSTAGE && CONFIG(ASAN_IN_RAMSTAGE)
_shadow_size = (_eheap - _data) >> 3;
REGION(asan_shadow, ., _shadow_size, ARCH_POINTER_ALIGN_SIZE)
#endif
_eprogram = .;
RECORD_SIZE(program)
/* Discard the sections we don't need/want */
zeroptr = 0;
/DISCARD/ : {
*(.comment)
*(.comment.*)
*(.note)
*(.note.*)
*(.eh_frame);
}
|
